14 resultados para IEEE 1451 standard

em WestminsterResearch - UK


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The I/Q mismatches in quadrature radio receivers results in finite and usually insufficient image rejection, degrading the performance greatly. In this paper we present a detailed analysis of the Blind-Source Separation (BSS) based mismatch corrector in terms of its structure, convergence and performance. The results indicate that the mismatch can be effectively compensated during the normal operation as well as in the rapidly changing environments. Since the compensation is carried out before any modulation specific processing, the proposed method works with all standard modulation formats and is amenable to low-power implementations.

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I and Q Channel phase and gain mismatches are of great concern in communications receiver design. In this paper we carry out a detailed performance analysis of the Blind-Source Seperation (BSS) based imbalance compensation structure. The results indicate that the BSS structure can offer adequate performance for most communication systems. Since the compensation is carried out before any modulation specific processing, the proposed compensation method works with all standard modulation formats.

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In this paper we carry out a detailed performance analysis of a novel blind-source-seperation (BSS) based DSP algorithm that tackles the carrier phase synchronization error problem. The results indicate that the mismatch can be effectively compensated during the normal operation as well as in the rapidly changing environments. Since the compensation is carried out before any modulation specific processing, the proposed method works with all standard modulation formats and lends itself to efficient real-time custom integrated hardware or software implementations.

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This paper presents a new design approach for a rail-to-rail bulk-driven input stage using a standard single-well (n-well in this paper) CMOS technology. This input stage can provide nearly constant transconductance and constant slew rate over the entire input common-mode voltage, operating with a wide supply voltage ranging from sub 1-volt (V/sub T0/+ 3V/sub DSsat/) to the maximum allowed for the CMOS process, as well as preventing latch-up.

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Polyphase IIR structures have recently proven themselves very attractive for very high performance filters that can be designed using very few coefficients. This, combined with their low sensitivity to coefficient quantization in comparison to standard FIR and IIR structures, makes them very applicable for very fast filtering when implemented in fixed-point arithmetic. However, although the mathematical description is very simple, there exist a number of ways to implement such filters. In this paper, we take four of these different implementation structures, analyze the rounding noise originating from the limited arithmetic wordlength of the mathematical operators, and check the internal data growth within the structure. These analyses need to be done to ensure that the performance of the implementation matches the performance of the theoretical design. The theoretical approach that we present has been proven by the results of the fixed-point simulation done in Simulink and verified by an equivalent bit-true implementation in VHDL.

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A simple but effective technique to improve the performance of the Max-Log-MAP algorithm is to scale the extrinsic information exchanged between two MAP decoders. A comprehensive analysis of the selection of the scaling factors according to channel conditions and decoding iterations is presented in this paper. Choosing a constant scaling factor for all SNRs and iterations is compared with the best scaling factor selection for changing channel conditions and decoding iterations. It is observed that a constant scaling factor for all channel conditions and decoding iterations is the best solution and provides a 0.2-0.4 dB gain over the standard Max- Log-MAP algorithm. Therefore, a constant scaling factor should be chosen for the best compromise.

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Turbo codes experience a significant decoding delay because of the iterative nature of the decoding algorithms, the high number of metric computations and the complexity added by the (de)interleaver. The extrinsic information is exchanged sequentially between two Soft-Input Soft-Output (SISO) decoders. Instead of this sequential process, a received frame can be divided into smaller windows to be processed in parallel. In this paper, a novel parallel processing methodology is proposed based on the previous parallel decoding techniques. A novel Contention-Free (CF) interleaver is proposed as part of the decoding architecture which allows using extrinsic Log-Likelihood Ratios (LLRs) immediately as a-priori LLRs to start the second half of the iterative turbo decoding. The simulation case studies performed in this paper show that our parallel decoding method can provide %80 time saving compared to the standard decoding and %30 time saving compared to the previous parallel decoding methods at the expense of 0.3 dB Bit Error Rate (BER) performance degradation.

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Two novel effective-fourth-order (eighth-order) resonator based MASH (MultistAge noise SHaping) bandpass Σ-Δ modulators are introduced at the behavioural level and subsequently examined by simulations utilising the ALTA SPW environment. The considered bandpass configurations have in their loop filter a cascade of standard second-order resonator structures in order to achieve appropriate noise shaping. The quantisation noise in each stage is suppressed by feeding the error of each section into the input of the following stage. It is demonstrated in this paper that the quadruple effective-first-order cascade configuration has significantly better performance as well as conforming more closely with theory in comparison with the effective-second-order effective-second-order cascade. The superior performance of the former can be attributed to the cumulative effect of the multi-bit outputs as well as the presence of more notch filters.

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This letter presents an ultra compact extracted pole E-plane filter. The proposed structure can achieve up to 65% size reduction in comparison with a standard extracted pole filter designed at 9.5 GHz centre frequency with a 3% fractional bandwidth. The filter has been fabricated and tested using E-plane waveguide technology. Measurements on a fabricated filter confirm the accuracy of the design method.

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A novel compact tunable bandstop filter using Defected Microstrip Structure (DMS) is presented in this paper. The structure utilizes a modified T shaped DMS which helps in miniaturization of the filter. To verify the concept, one such filter was simulated, designed, fabricated and tested. Measurements on a fabricated tunable filter confirm the accuracy of the design procedure. The tuning range of 20% is achieved, ranging from 2.26 GHz to 2.747 GHz. Tuning is achieved by using NXP BB179 varactor diode. A nonlinear distortion evaluation in a tunable filter was experimentally verified. Experimental verification shows the filter is highly linear.

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The general election of 29 October 1924 saw Winston Churchill return to Parliament as Constitutionalist MP for Epping after two years in the political wilderness. It also saw Stanley Baldwin swept back to Number 10 on a Conservative landslide. Speculation about whether Baldwin would cement Churchill’s drift from the Liberal fold by offering him office surfaced during the election campaign. Churchill nevertheless thought ‘it very unlikely that I shall be invited to join the Government, as owing to the size of the majority it will probably be composed only of impeccable Conservatives’. [ 1 ] Because of his anti-socialist credentials, his ability to reassure wavering Liberals through his opposition to protectionism – dropped by Baldwin after its rejection in the 1923 general election – and concern he could prove a rallying point for backbench malcontents, there was however much to commend giving Churchill a post. To his surprise, Baldwin offered Churchill the long-coveted office of Chancellor of the Exchequer, briefly held by his father before his ill-conceived resignation in 1887. Having arranged a meeting with his Labour predecessor, Philip Snowden, about outstanding business the new Chancellor set to work. Marking his political transition, a few days later Churchill resigned from the National Liberal Club.

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This revisits Churchill's decision, as Chancellor of the Exchequer 1924-29, to restore the Gold Standard in 1925. This is considered within the wider context of the overall aims of Churchill's policies, including his efforts to: tackle Anglo-American economic and financial relations in the aftermath of the Great War; address budgetary pressures; widen the tax base through innovations such as the Betting Duty; spread the social burden of taxes; and revive the economy, not least through his de-rating scheme.

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The present study examined the factorial and construct validity of a Standard Chinese translation of the Body Appreciation Scale (BAS-2; Tylka & Wood-Barcalow, 2015b). Participants were 191 women and 154 men from mainland China who were resident in Hong Kong at the time of recruitment. Results of confirmatory factor analysis indicated that the one-dimensional model of the BAS-2, in which all 10 items loaded onto the same factor, had adequate fit and was invariant across sex. Body appreciation scores had good internal consistency and were significantly correlated with self-esteem and life satisfaction, and, in women, with weight discrepancy and body mass index. There were no significant differences in body appreciation scores between women and men. The present findings suggest that the Standard Chinese translation of the BAS-2 has the same one-dimensional factor structure as its parent scale and may facilitate cross-cultural studies of positive body image.