MASH structures for bandpass sigma-delta modulators

The paper presents simulation results from investigating the behaviour of multistage (MASH) oversampled bandpass sigma-delta (Σ-Δ) modulators for use in analogue to digital converters for high frequency narrowband applications such as the signals out of the intermediate frequency (IF) section of a superheterodyne radio receiver. The bandpass configurations under consideration have in their loop filter a cascade of second-order resonator structures in order to achieve acceptable noise shaping. The quantisation noise in each stage is suppressed by feeding the error of each section into the input of the following stages. It is demonstrated that the triple effective-first-order bandpass MASH structure has significantly better performance compared with the effective-second-order effective-first-order bandpass MASH structure.

Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators

In this thesis, novel analog-to-digital and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable bandpass sigma-delta modulators can perform noise-shaping for any centre frequency from DC to Nyquist. The proposed topologies are well-suited for Butterworth, Chebyshev, inverse-Chebyshev and elliptical filters, where designers have the flexibility of specifying the centre frequency, bandwidth as well as the passband and stopband attenuation parameters. The application of the time-interleaving approach, in combination with these bandpass loop-filters, not only overcomes the limitations that are associated with conventional and mid-band resonator-based bandpass sigma-delta modulators, but also offers an elegant means to increase the conversion bandwidth, thereby relaxing the need to use faster or higher-order sigma-delta modulators. A step-by-step design technique has been developed for the design of time-interleaved variable bandpass sigma-delta modulators. Using this technique, an assortment of lower- and higher-order single- and multi-path generalized A/D variable bandpass sigma-delta modulators were designed, evaluated and compared in terms of their signal-to-noise ratios, hardware complexity, stability, tonality and sensitivity for ideal and non-ideal topologies. Extensive behavioural-level simulations verified that one of the proposed topologies not only used fewer coefficients but also exhibited greater robustness to non-idealties. Furthermore, second-, fourth- and sixth-order single- and multi-path digital variable bandpass digital sigma-delta modulators are designed using this technique. The mathematical modelling and evaluation of tones caused by the finite wordlengths of these digital multi-path sigmadelta modulators, when excited by sinusoidal input signals, are also derived from first principles and verified using simulation and experimental results. The fourth-order digital variable-band sigma-delta modulator topologies are implemented in VHDL and synthesized on Xilinx® SpartanTM-3 Development Kit using fixed-point arithmetic. Circuit outputs were taken via RS232 connection provided on the FPGA board and evaluated using MATLAB routines developed by the author. These routines included the decimation process as well. The experiments undertaken by the author further validated the design methodology presented in the work. In addition, a novel tunable and reconfigurable second-order variable bandpass sigma-delta modulator has been designed and evaluated at the behavioural-level. This topology offers a flexible set of choices for designers and can operate either in single- or dual-mode enabling multi-band implementations on a single digital variable bandpass sigma-delta modulator. This work is also supported by a novel user-friendly design and evaluation tool that has been developed in MATLAB/Simulink that can speed-up the design, evaluation and comparison of analog and digital single-stage and time-interleaved variable bandpass sigma-delta modulators. This tool enables the user to specify the conversion type, topology, loop-filter type, path number and oversampling ratio.

Effective-fourth-order resonator based MASH bandpass sigma-delta modulators

Two novel effective-fourth-order (eighth-order) resonator based MASH (MultistAge noise SHaping) bandpass Σ-Δ modulators are introduced at the behavioural level and subsequently examined by simulations utilising the ALTA SPW environment. The considered bandpass configurations have in their loop filter a cascade of standard second-order resonator structures in order to achieve appropriate noise shaping. The quantisation noise in each stage is suppressed by feeding the error of each section into the input of the following stage. It is demonstrated in this paper that the quadruple effective-first-order cascade configuration has significantly better performance as well as conforming more closely with theory in comparison with the effective-second-order effective-second-order cascade. The superior performance of the former can be attributed to the cumulative effect of the multi-bit outputs as well as the presence of more notch filters.

Narrow-band variable center frequency single-loop and multistage sigma-delta modulators for bandpass signals

Oversampled narrow-band single-loop and multistage resonator-based bandpass sigma-delta (Σ-Δ) modulators that can accommodate different passband center to sampling frequency ratios are reported. These tunable bandpass configurations are designed by analytically determining and subsequently verifying through detailed empirical simulations the required compensation hardware to deliver enhanced noise-shaping. It is demonstrated that comparatively superior in-band signal-to-noise ratios and dynamic ranges are attributed to the inclusion of appropriate digital feedforward and feedback compensators within these structures.

An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.