Compensation of undesired effects in MIMO wireless transceivers

This paper presents compensation of all undesired effects (Power Amplifier (PA) nonlinearity, transmitter and receiver antenna crosstalk, before-PA nonlinear crosstalk, Multiple Input Multiple Output (MIMO) channel fading and crosstalk) in MIMO Orthogonal Frequency Division Multiplex (OFDM) wireless systems. It has been demonstrated that reduced-complexity Crossover Digital Predistortion (CO-DPD) algorithm on transmitter side and Matrix Inversion algorithm on receiver side can suppress almost all undesired effects introduced by transmitter, channel and receiver in 4×4 MIMO OFDM System that can be used in modern wireless system applications. A significant complexity reduction is achieved due to the fact that Digital Signal Processing (DSP) during CO-DPD process on transmitter side is done with real instead of complex numbers.

A low-complexity self-calibrating adaptive quadrature receiver

In this paper digital part of a self-calibrating quadrature-receiver is described, containing a digital calibration-engine. The blind source-separation-based calibration-engine eliminates the RF-impairments in real-time hence improving the receiver's performance without the need for test/pilot tones, trimming or use of power-hungry discrete components. Furthermore, an efficient time-multiplexed calibration-engine architecture is proposed and implemented on an FPGA utilising a reduced-range multiplier structure. The use of reduced-range multipliers results in substantial reduction of area as well as power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier. The performance of the calibration-engine does not depend on the modulation format or the constellation size of the received signal; hence it can be easily integrated into the digital signal processing paths of any receiver.

Living and dealing with RF impairments in communication transceivers

This paper provides an overview of the sources and effects of the RF impairments limiting and rendering the performance of the future wireless communication transceivers costly as well as hindering their wide-spread use in commercial products. As transmission bandwidths and carrier frequencies increase effect of these impairments worsen. This paper studies and presents analytical evaluations of the performance degradation due to the RF impairments in terms of bit-error-rate and image rejection ratio. The paper also give highlights of the various aspects of the research carried out in mitigating the effects of these impairments primarily in the digital signal processing domain at the baseband as well as providing low-complexity hardware implementations of such algorithms incorporating a number of power and area saving techniques.

MASH structures for bandpass sigma-delta modulators

The paper presents simulation results from investigating the behaviour of multistage (MASH) oversampled bandpass sigma-delta (Σ-Δ) modulators for use in analogue to digital converters for high frequency narrowband applications such as the signals out of the intermediate frequency (IF) section of a superheterodyne radio receiver. The bandpass configurations under consideration have in their loop filter a cascade of second-order resonator structures in order to achieve acceptable noise shaping. The quantisation noise in each stage is suppressed by feeding the error of each section into the input of the following stages. It is demonstrated that the triple effective-first-order bandpass MASH structure has significantly better performance compared with the effective-second-order effective-first-order bandpass MASH structure.

Adaptive self-calibrating image rejection receiver

An adaptive self-calibrating image rejection receiver is described, containing a modified Weaver image rejection mixer and a Digital Image Rejection Processor (DIRP). The blind source-separation-based DIRP eliminates the I/Q errors improving the Image Rejection Ratio (IRR) without the need for trimming or use of power-hungry discrete components. Hardware complexity is minimal, requiring only two complex coefficients; hence it can be easily integrated into the signal processing path of any receiver. Simulation results show that the proposed approach achieves 75-97 dB of IRR.

Adaptive digital receivers for analog front-end mismatch correction

Phase and gain mismatches between the I and Q analog signal processing paths of a quadrature receiver are responsible for the generation of image signals which limit the dynamic range of a practical receiver. In this paper we analyse the effects these mismatches and propose a low-complexity blind adaptive algorithm to minimize this problem. The proposed solution is based on two, 2-tap adaptive filters, arranged in Adaptive Noise Canceller (ANC) set-up. The algorithm lends itself to efficient real-time implementation with minimal increase in modulator complexity.

A computationally efficient DAB bit-stream processor

This paper describes an MPEG (moving pictures expert group) audio layer II - LFE (lower frequency extension) bit-stream processor targeting DAB (digital audio broadcasting) receivers that will handle the decoding of the frames in a computationally efficient manner to provide a synthesis sub-band filter with the reconstructed sub-band samples. Focus is given to the frequency sample reconstruction part, which handles the re-quantization and re-scaling of the samples once the necessary information is extracted from the frame. The comparison to a direct implementation of the frequency sample reconstruction block is carried out to prove increased computational efficiency.

An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.