6 resultados para Continuous flight envelope

em WestminsterResearch - UK


Relevância:

20.00% 20.00%

Publicador:

Resumo:

Next generation Global Navigation Satellite System (GNSS) receivers will operate in multiple navigation bands. An efficient way to achieve this with lower power and cost is to employ BandPass Sampling (BPS); nevertheless, the sampling operation injects large amounts of jitter noise, which degrades the performance of the receiver. Continuous–Time (CT) Delta–Sigma (ΔΣ) modulators are capable of suppressing this noise but the impact of clock jitter at the output of the Digital– to–Analog Converter (DAC) in the feedback path of the modulator should be taken into account. This paper presents an analytical approach for describing clock jitter in GNSS receivers when a CT–ΔΣ modulator is utilized for Analog–to–Digital Conversion (ADC). The validity of the presented approach is verified through time–domain simulations using a behavioural model of the fourth–order CT–ΔΣ modulator with 1–bit NRZ DAC feedback pulse.

Relevância:

20.00% 20.00%

Publicador:

Resumo:

This paper applies Gaussian estimation methods to continuous time models for modelling overseas visitors into the UK. The use of continuous time modelling is widely used in economics and finance but not in tourism forecasting. Using monthly data for 1986–2010, various continuous time models are estimated and compared to autoregressive integrated moving average (ARIMA) and autoregressive fractionally integrated moving average (ARFIMA) models. Dynamic forecasts are obtained over different periods. The empirical results show that the ARIMA model performs very well, but that the constant elasticity of variance (CEV) continuous time model has the lowest root mean squared error (RMSE) over a short period.

Relevância:

20.00% 20.00%

Publicador:

Resumo:

Sweroside, a major active iridoid in Swertia pseudochinensis Hara, is recognized as an effective agent in the treatment of liver injury. Based on previous reports, the relatively short half-life (64 min) and poor bioavailability (approximately 0.31%) in rats suggested that not only sweroside itself but also its metabolites could be responsible for the observed hepato-protective effect. However, few studies have been carried out on the metabolism of sweroside. Therefore, the present study aimed at identifying the metabolites of sweroside in rat urine after a single oral dose (100 mg/kg). With ultra-high-performance liquid chromatography coupled with electrospray ionization quadrupole time-of-flight tandem mass spectrometry (UHPLC/Q-TOF-MS), the metabolic profile revealed 11 metabolites in rat urine, including phase I, phase II and aglycone-related products. The chemical structures of metabolites were proposed based on accurate mass measurements of protonated or deprotonated molecules and their fragmentation patterns. Our findings showed that the aglycone of sweroside (M05) and its glucuronide conjugate (M06) were principal circulating metabolites in rats. While several other metabolic transformations, occurring via reduction, N-heterocyclization and N-acetylation after deglycosylation, were also observed. Two metabolites (M05 and M06) were isolated from the rat urine for structural elucidation and identifcation of reaction sites. Both M05 and M06 were characterized by 1H, 13C and two-dimensional nuclear magnetic resonance (NMR) spectroscopy. UHPLC/Q-TOF-MS analysis has provided an important analytical platform to gather metabolic profile of sweroside.

Relevância:

20.00% 20.00%

Publicador:

Resumo:

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.