Urban design, central London and the ‘crisis’ 2007-2013: business as usual?

London is changing, to a breath-taking extent. Beneath this fast paced activity, new patterns are forming and divisions that had been relatively unremarked before are now becoming increasingly visible. The ‘square mile’ of the City of London, which is now identified by some dramatically tall buildings, forms a contrast to the traditional urbanism of the City of Westminster, the majority of which is covered by conservation area legislation. This paper will consider this contrast from the perspective of urban design, examining both the wider development context for these changes and the separate design policies of these two historic organisations of local government. One of the key questions to be investigated is how these changes have impacted on the character of central London as a place. Moving on from the well-rehearsed debates about London’s skyline, the paper considers the significance of urban design in the context of a global urban spatial economy. It suggests that central London faces severe dilemmas about its future if the growth scenario continues.

An FPGA based decimation filter processor design for real-time continuous-time Σ−Δ modulator performance measurement and evaluation

This paper reports on a Field Programmable Gate Array (FPGA) implementation as well as prototyping for real-time testing of a low complexity high efficiency decimation filter processor which is deployed in conjunction with a custom built low-power jitter insensitive Continuous Time (CT) Sigma-Delta (Σ-Δ) Modulator to measure and assess its performance. The CT Σ-Δ modulator/decimation filter cascade can be used in integrated all-digital microphone interfaces for a variety of applications including mobile phone handsets, wireless handsets as well as other applications requiring all-digital microphones. The work reported here concentrates on the design and implementation as well as prototyping on a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying All-Pass based structures to process the bit stream coming from CT Σ-Δ modulator hence measuring in real-time and fully assessing the modulator's performance.