4 resultados para cascade of pi-circuits

em Universidad de Alicante


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Thermal decomposition of printed circuits boards (PCB) is studied, using thermogravimetric analysis to compare the thermal behavior of PCB of mobile phones before and after the removal of the metallic fraction by acid washing. Several dynamic and dynamic + isothermal runs have been carried out at different heating rates (5, 10 and 20 K min−1), from room temperature to more than 1100 K. Also runs in the presence and in the absence of oxygen were performed (combustion and pyrolysis runs). Moreover, TG–MS experiments were performed (both in inert and oxidizing atmosphere) in order to better understand the thermal decomposition of these wastes and identify some compounds emitted during the controlled heating of these materials. Different reaction models are proposed, one for pyrolysis and one for combustion of the two kinds of wastes studied, which proved to simulate appropriately the experimental results at all the heating rates simultaneously.

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We have studied the radial dependence of the energy deposition of the secondary electron generated by swift proton beams incident with energies T = 50 keV–5 MeV on poly(methylmethacrylate) (PMMA). Two different approaches have been used to model the electronic excitation spectrum of PMMA through its energy loss function (ELF), namely the extended-Drude ELF and the Mermin ELF. The singly differential cross section and the total cross section for ionization, as well as the average energy of the generated secondary electrons, show sizeable differences at T ⩽ 0.1 MeV when evaluated with these two ELF models. In order to know the radial distribution around the proton track of the energy deposited by the cascade of secondary electrons, a simulation has been performed that follows the motion of the electrons through the target taking into account both the inelastic interactions (via electronic ionizations and excitations as well as electron-phonon and electron trapping by polaron creation) and the elastic interactions. The radial distribution of the energy deposited by the secondary electrons around the proton track shows notable differences between the simulations performed with the extended-Drude ELF or the Mermin ELF, being the former more spread out (and, therefore, less peaked) than the latter. The highest intensity and sharpness of the deposited energy distributions takes place for proton beams incident with T ~ 0.1–1 MeV. We have also studied the influence in the radial distribution of deposited energy of using a full energy distribution of secondary electrons generated by proton impact or using a single value (namely, the average value of the distribution); our results show that differences between both simulations become important for proton energies larger than ~0.1 MeV. The results presented in this work have potential applications in materials science, as well as hadron therapy (due to the use of PMMA as a tissue phantom) in order to properly consider the generation of electrons by proton beams and their subsequent transport and energy deposition through the target in nanometric scales.

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Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best trade-offs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.

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The design of fault tolerant systems is gaining importance in large domains of embedded applications where design constrains are as important as reliability. New software techniques, based on selective application of redundancy, have shown remarkable fault coverage with reduced costs and overheads. However, the large number of different solutions provided by these techniques, and the costly process to assess their reliability, make the design space exploration a very difficult and time-consuming task. This paper proposes the integration of a multi-objective optimization tool with a software hardening environment to perform an automatic design space exploration in the search for the best trade-offs between reliability, cost, and performance. The first tool is commanded by a genetic algorithm which can simultaneously fulfill many design goals thanks to the use of the NSGA-II multi-objective algorithm. The second is a compiler-based infrastructure that automatically produces selective protected (hardened) versions of the software and generates accurate overhead reports and fault coverage estimations. The advantages of our proposal are illustrated by means of a complex and detailed case study involving a typical embedded application, the AES (Advanced Encryption Standard).