A Ku-band active transmit-array module with a horn or patch array as a signal launching/receiving device

This paper is concerned with the design of a Ku-band active transmit-array module of transistor amplifiers excited by either a pyramidal horn or a patch array Optimal distances between the active transmit array and the signal-launching:receiving device, which is either a passive corporate-fed array or a horn, are determined to maximise the power gain at a design frequency: Having established these conditions, the complete structure is investigated in terms of operational bandwidth and near-field and far-field distributions measured at the output side of the transmit array, The experimental results show that the use of a corporate-fed array as an illuminating/receiving device gives higher gain and significantly larger operational bandwidth, An explanation for this behavior is sought.

Functionally partitioned module-based programmable architecture for wireless base-band processing

A specialised reconfigurable architecture is targeted at wireless base-band processing. It is built to cater for multiple wireless standards. It has lower power consumption than the processor-based solution. It can be scaled to run in parallel for processing multiple channels. Test resources are embedded on the architecture and testing strategies are included. This architecture is functionally partitioned according to the common operations found in wireless standards, such as CRC error correction, convolution and interleaving. These modules are linked via Virtual Wire Hardware modules and route-through switch matrices. Data can be processed in any order through this interconnect structure. Virtual Wire ensures the same flexibility as normal interconnects, but the area occupied and the number of switches needed is reduced. The testing algorithm scans all possible paths within the interconnection network exhaustively and searches for faults in the processing modules. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This paper compares various base-band processing solutions. It describes the proposed platform and its implementation. It outlines the test resources and algorithm. It concludes with the mapping of Bluetooth and GSM base-band onto the platform.

PhotoVoltaic DC-DC module integrated converter for novel cascaded and bypass grid connection topologies - design and optimisation

Grid connected PhotoVoltaic (PV) inverters fall into three broad categories — Central, String and Module Integrated Converers (MICs). MICs offer any avantaes in performance and flexibility, but are at a cost disadvantage. Two alternative novel approaches proposed by the author — cascaded dc-dc MICs and bypass dc-dc MICs — integrate a simple non-isolated intelligent dc-dc converter with each PV module to provide the advantages of dc-ac MICs at a lower cost. A suitable universal 150W 5A dc-dc converter design is presented based on two interleaved MOSFET half bridges. Testing shows Zero Voltage Switching (ZVS) keeps losses under 1W for bi-directional power flows up to 15W between two adjacent 12V PV modules for the bypass application, and efficiencies over 94% for most of the operational power range for the cascaded converter application. Based on the experimental results, potential optimizations to further reduce losses are discussed.