The personality profile of female Anglican clergy in Britain and Ireland: A study employing the Eysenck Personality Profiler

A sample of 523 newly ordained female Anglican clergy in England, Ireland, Scotland and Wales completed the Eysenck Personality Profiler (EPP). The data demonstrated that the female clergy tended to be less extravert than women in general, less neurotic than women in general, and less toughminded than women in general. These findings help to clarify the way in which women clergy tend to project a characteristically masculine personality profile in respect of one major dimension of personality (neuroticism), but a characteristically feminine personality profile in respect of the other two major dimensions of personality (psychoticism and extraversion).

Investigations into a wideband spatial beamformer employing a rectangular array of planar monopoles

This paper presents a rectangular array antenna with a suitable signal-processing algorithm that is able to steer the beam in azimuth over a wide frequency band. In the previous approach, which was reported in the literature, an inverse discrete Fourier transform technique was proposed for obtaining the signal weighting coefficients. This approach was demonstrated for large arrays in which the physical parameters of the antenna elements were not considered. In this paper, a modified signal-weighting algorithm that works for arbitrary-size arrays is described. Its validity is demonstrated in examples of moderate-size arrays with real antenna elements. It is shown that in some cases, the original beam-forming algorithm fails, while the new algorithm is able to form the desired radiation pattern over a wide frequency band. The performance of the new algorithm is assessed for two cases when the mutual coupling between array elements is both neglected and taken into account.

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving fitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.