Fast nonadiabatic two-qubit gates for the Kane quantum computer

In this paper, we apply the canonical decomposition of two-qubit unitaries to find pulse schemes to control the proposed Kane quantum computer. We explicitly find pulse sequences for the controlled-NOT, swap, square root of swap, and controlled Z rotations. We analyze the speed and fidelity of these gates, both of which compare favorably to existing schemes. The pulse sequences presented in this paper are theoretically faster, with higher fidelity, and simpler. Any two-qubit gate may be easily found and implemented using similar pulse sequences. Numerical simulation is used to verify the accuracy of each pulse scheme.

Quantum-error correction on linear-nearest-neighbor qubit arrays

A quantum circuit implementing 5-qubit quantum-error correction on a linear-nearest-neighbor architecture is described. The canonical decomposition is used to construct fast and simple gates that incorporate the necessary swap operations allowing the circuit to achieve the same depth as the current least depth circuit. Simulations of the circuit's performance when subjected to discrete and continuous errors are presented. The relationship between the error rate of a physical qubit and that of a logical qubit is investigated with emphasis on determining the concatenated error correction threshold.

Gates for the kane quantum computer in the presence of dephasing

In this paper we investigate the effect of dephasing on proposed quantum gates for the solid-state Kane quantum computing architecture. Using a simple model of the decoherence, we find that the typical error in a controlled-NOT gate is 8.3x10(-5). We also compute the fidelities of Z, X, swap, and controlled Z operations under a variety of dephasing rates. We show that these numerical results are comparable with the error threshold required for fault tolerant quantum computation.

ADSL transceivers applying DSM and their nonstationary noise robustness

Dynamic spectrum management (DSM) comprises a new set of techniques for multiuser power allocation and/or detection in digital subscriber line (DSL) networks. At the Alcatel Research and Innovation Labs, we have recently developed a DSM test bed, which allows the performance of DSM algorithms to be evaluated in practice. With this test bed, we have evaluated the performance of a DSM level-1 algorithm known as iterative water-filling in an ADSL scenario. This paper describes the results of, on the one hand, the performance gains achieved with iterative water-filling, and, on the other hand, the nonstationary noise robustness of DSM-enabled ADSL modems. It will be shown that DSM trades off nonstationary noise robustness for performance improvements. A new bit swap procedure is then introduced to increase the noise robustness when applying DSM.

Formalising progress properties of non-blocking programs

A non-blocking program is one that uses non-blocking primitives, such as load-linked/store-conditional and compare-and-swap, for synchronisation instead of locks so that no process is ever blocked. According to their progress properties, non-blocking programs may be classified as wait-free, lock-free or obstruction-free. However, a precise description of these properties does not exist and it is not unusual to find a definition that is ambiguous or even incorrect. We present a formal definition of the progress properties so that any confusion is removed. The formalisation also allows one to prove the widely believed presumption that wait-freedom is a special case of lock-freedom, which in turn is a special case of obstruction-freedom.