3 resultados para Polynomial time hierarchy

em University of Queensland eSpace - Australia


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Hannenhalli and Pevzner developed the first polynomial-time algorithm for the combinatorial problem of sorting of signed genomic data. Their algorithm solves the minimum number of reversals required for rearranging a genome to another when gene duplication is nonexisting. In this paper, we show how to extend the Hannenhalli-Pevzner approach to genomes with multigene families. We propose a new heuristic algorithm to compute the reversal distance between two genomes with multigene families via the concept of binary integer programming without removing gene duplicates. The experimental results on simulated and real biological data demonstrate that the proposed algorithm is able to find the reversal distance accurately. ©2005 IEEE

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Complementing our recent work on subspace wavepacket propagation [Chem. Phys. Lett. 336 (2001) 149], we introduce a Lanczos-based implementation of the Faber polynomial quantum long-time propagator. The original version [J. Chem. Phys. 101 (1994) 10493] implicitly handles non-Hermitian Hamiltonians, that is, those perturbed by imaginary absorbing potentials to handle unwanted reflection effects. However, like many wavepacket propagation schemes, it encounters a bottleneck associated with dense matrix-vector multiplications. Our implementation seeks to reduce the quantity of such costly operations without sacrificing numerical accuracy. For some benchmark scattering problems, our approach compares favourably with the original. (C) 2004 Elsevier B.V. All rights reserved.

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This paper explores potential for the RAMpage memory hierarchy to use a microkernel with a small memory footprint, in a specialized cache-speed static RAM (tightly-coupled memory, TCM). Dreamy memory is DRAM kept in low-power mode, unless referenced. Simulations show that a small microkernel suits RAMpage well, in that it achieves significantly better speed and energy gains than a standard hierarchy from adding TCM. RAMpage, in its best 128KB L2 case, gained 11% speed using TCM, and reduced energy 14%. Equivalent conventional hierarchy gains were under 1%. While 1MB L2 was significantly faster against lower-energy cases for the smaller L2, the larger SRAM's energy does not justify the speed gain. Using a 128KB L2 cache in a conventional architecture resulted in a best-case overall run time of 2.58s, compared with the best dreamy mode run time (RAMpage without context switches on misses) of 3.34s, a speed penalty of 29%. Energy in the fastest 128KB L2 case was 2.18J vs. 1.50J, a reduction of 31%. The same RAMpage configuration without dreamy mode took 2.83s as simulated, and used 2.39J, an acceptable trade-off (penalty under 10%) for being able to switch easily to a lower-energy mode.