2 resultados para Phase error
em University of Queensland eSpace - Australia
Resumo:
The design of an X-band tray-type spatial power combiner, which employs uniplanar quasi-Yagi antennas (QYAs) for receiving and transmitting signals by individual amplifiers, is presented. Passive and active varieties of a seven-tray power-combining structure that includes two hard horns for uniform signal launching and combining across the tray stack are developed and measured. In order to compensate for nonuniform phase across the stack, which is caused by the nonplanar wave front of the horn antennas, Schiffman phase shifters are implemented in individual trays. The experimental-results show an improved performance of the investigated tray-type power combiner when the proposed phase-error compensation is implemented. (C) 2004 Wiley Periodicals, Inc.
Resumo:
Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving fitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.