Voltage control of exchange coupling in phosphorus doped silicon

Motivated by applications to quantum computer architectures we study the change in the exchange interaction between neighbouring phosphorus donor electrons in silicon due to the application of voltage biases to surface control electrodes. These voltage biases create electro-static fields within the crystal substrate, perturbing the states of the donor electrons and thus altering the strength of the exchange interaction between them. We find that control gates of this kind can be used to either enhance or reduce the strength of the interaction, by an amount that depends both on the magnitude and orientation of the donor separation.

High-fidelity measurement and quantum feedback control in circuit QED

Circuit QED is a promising solid-state quantum computing architecture. It also has excellent potential as a platform for quantum control-especially quantum feedback control-experiments. However, the current scheme for measurement in circuit QED is low efficiency and has low signal-to-noise ratio for single-shot measurements. The low quality of this measurement makes the implementation of feedback difficult, and here we propose two schemes for measurement in circuit QED architectures that can significantly improve signal-to-noise ratio and potentially achieve quantum-limited measurement. Such measurements would enable the implementation of quantum feedback protocols and we illustrate this with a simple entanglement-stabilization scheme.

A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving fitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.

Formal change impact analyses for emulated control software

Processor emulators are a software tool for allowing legacy computer programs to be executed on a modern processor. In the past emulators have been used in trivial applications such as maintenance of video games. Now, however, processor emulation is being applied to safety-critical control systems, including military avionics. These applications demand utmost guarantees of correctness, but no verification techniques exist for proving that an emulated system preserves the original system’s functional and timing properties. Here we show how this can be done by combining concepts previously used for reasoning about real-time program compilation, coupled with an understanding of the new and old software architectures. In particular, we show how both the old and new systems can be given a common semantics, thus allowing their behaviours to be compared directly.