A green perspective on Structured parallel programming

Structured parallel programming, and in particular programming models using the algorithmic skeleton or parallel design pattern concepts, are increasingly considered to be the only viable means of supporting effective development of scalable and efficient parallel programs. Structured parallel programming models have been assessed in a number of works in the context of performance. In this paper we consider how the use of structured parallel programming models allows knowledge of the parallel patterns present to be harnessed to address both performance and energy consumption. We consider different features of structured parallel programming that may be leveraged to impact the performance/energy trade-off and we discuss a preliminary set of experiments validating our claims.

Creating New Design-Build-Test Experiences as Outputs of Undergraduate Design-Build-Test Projects

This paper describes a methodology of using individual engineering undergraduate student projects as a means of effectively and efficiently developing new Design-Build-Test (DBT) learning experiences and challenges.
A key aspect of the rationale for this approach is that it benefits all parties. The student undertaking the individual project gets an authentic experience of producing a functional artefact, which has been the result of a design process that addresses conception, design, implementation and operation. The supervising faculty member benefits from live prototyping of new curriculum content and resources with a student who is at a similar level of knowledge and experience as the intended end users of the DBT outputs. The multiple students who ultimately undertake the DBT experiences / challenges benefit from the enhanced nature of a learning experience which has been “road tested” and optimised.
To demonstrate the methodology the paper will describe a case study example of an individual project completed in 2015. This resulted in a DBT design challenge with a theme of designing a catapult for throwing table tennis balls, the device being made from components laser cut from medium density fibreboard (MDF). Further three different modes of operation will be described which use the same resource materials but operate over different timescales and with different learning outcomes, from an icebreaker exercise focused on developing team dynamics through to full DBT where students get an opportunity to experience the full impact of their design decisions by competing against other students with a catapult they have designed and built themselves.

VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform

This paper proposes a JPEG-2000 compliant architecture capable of computing the 2 -D Inverse Discrete Wavelet Transform. The proposed architecture uses a single processor and a row-based schedule to minimize control and routing complexity and to ensure that processor utilization is kept at 100%. The design incorporates the handling of borders through the use of symmetric extension. The architecture has been implemented on the Xilinx Virtex2 FPGA.

Experimental Study on Key Generation for Physical Layer Security in Wireless Communications

This paper presents a thorough experimental study on key generation principles, i.e. temporal variation, channel reciprocity, and spatial decorrelation, via a testbed constructed by using wireless open-access research platform (WARP). It is the first comprehensive study through (i) carrying out a number of experiments in different multipath environments, including an anechoic chamber, a reverberation chamber and an indoor office environment, which represents little, rich, and moderate multipath, respectively; (ii) considering static, object moving, and mobile scenarios in these environments, which represents different levels of channel dynamicity; (iii) studying two most popular channel parameters, i.e., channel state information and received signal strength. Through results collected from over a hundred tests, this paper offers insights to the design of a secure and efficient key generation system. We show that multipath is essential and beneficial for key generation as it increases the channel randomness. We also find that the movement of users/objects can help introduce temporal variation/randomness and help users reach an agreement on the keys. This paper complements existing research by experiments constructed by a new hardware platform.

The Evolution of 'Design Build Fly' Led Teaching in Aerospace Engineering

This paper describes the evolution of a ‘Design - Build-Fly’ (DBF) approach to the delivery and assessment of a Stage Three Aircraft Design module. It focuses on the primary learning outcomes around the design and manufacturing functions associated with the development of a remotely controlled aircraft. The work covers a six year period from 2011 to present mapping the transformation of the module from report based assessment to a more hands on approach resulting in a fully functioning remotely controlled aircraft. Results show that both the staff and student experience improved across key performance metrics including student feedback, learning and competency development. Challenges still remain in methods of placing students within teams and maintaining technical rigour in reporting as students develop vocational skills and more reflective writing styles.

Circuit-aware design of energy-efficient massive MIMO systems

Densification is a key to greater throughput in cellular networks. The full potential of coordinated multipoint (CoMP) can be realized by massive multiple-input multiple-output (MIMO) systems, where each base station (BS) has very many antennas. However, the improved throughput comes at the price of more infrastructure; hardware cost and circuit power consumption scale linearly/affinely with the number of antennas. In this paper, we show that one can make the circuit power increase with only the square root of the number of antennas by circuit-aware system design. To this end, we derive achievable user rates for a system model with hardware imperfections and show how the level of imperfections can be gradually increased while maintaining high throughput. The connection between this scaling law and the circuit power consumption is established for different circuits at the BS.

Enhancing the Manufacturing Knowledge of Undergraduate Engineering Students: A Case Study of a Design-Build-Test Challenge Involving Folding Bicycles

Many engineers currently in professional practice will have gained a degree level qualification which involved studying a curriculum heavy with mathematics and engineering science. While this knowledge is vital to the engineering design process so also is manufacturing knowledge, if the resulting designs are to be both technically and commercially viable.
The methodology advanced by the CDIO Initiative aims to improve engineering education by teaching in the context of Conceiving, Designing, Implementing and Operating products, processes or systems. A key element of this approach is the use of Design-Built-Test (DBT) projects as the core of an integrated curriculum. This approach facilitates the development of professional skills as well as the application of technical knowledge and skills developed in other parts of the degree programme. This approach also changes the role of lecturer to that of facilitator / coach in an active learning environment in which students gain concrete experiences that support their development.
The case study herein describes Mechanical Engineering undergraduate student involvement in the manufacture and assembly of concept and functional prototypes of a folding bicycle.

Time-Independent Discrete Gaussian Sampling for Post-Quantum Cryptography

As the development of a viable quantum computer nears, existing widely used public-key cryptosystems, such as RSA, will no longer be secure. Thus, significant effort is being invested into post-quantum cryptography (PQC). Lattice-based cryptography (LBC) is one such promising area of PQC, which offers versatile, efficient, and high performance security services. However, the vulnerabilities of these implementations against side-channel attacks (SCA) remain significantly understudied. Most, if not all, lattice-based cryptosystems require noise samples generated from a discrete Gaussian distribution, and a successful timing analysis attack can render the whole cryptosystem broken, making the discrete Gaussian sampler the most vulnerable module to SCA. This research proposes countermeasures against timing information leakage with FPGA-based designs of the CDT-based discrete Gaussian samplers with constant response time, targeting encryption and signature scheme parameters. The proposed designs are compared against the state-of-the-art and are shown to significantly outperform existing implementations. For encryption, the proposed sampler is 9x faster in comparison to the only other existing time-independent CDT sampler design. For signatures, the first time-independent CDT sampler in hardware is proposed.