109 resultados para bis-GMA analog
Resumo:
We describe new methodology for the synthesis of symmetric bis-benzimidazole carrying 2-aryl moieties, including 2-[4-3'-aminopropoxy)phenyl] and 2-[4-(3'-aminopropanamido)pheny] substituents, together with the synthesis of novel hybrid molecules comprising bis-benzimidazoles in ester and amide combination with the N-mustard chlorambucil. The in vitro activities of these compounds against five cancer cell lines are also provided.
Resumo:
A new generation of water soluble tetrazolium salts have recently become available and in this study we compared a colorimetric assay developed using one of these salts, 2-(2-methoxy-4-nitrophenyl)-3-(4-nitrophenyl)-5-(2, 4-disulfophenyl)-2H-tetrazolium, monosodium salt (WST-8), with a previously developed 2,3-bis[2-methyloxy-4-nitro-5-sulfophenyl]-2H-tetrazolium-5-carboxanilide(XTT) colorimetric assay to determine which agent is most suitable for use as a colorimetric indicator in susceptibility testing. The MICs of 6 antibiotics were determined for 33 staphylococci using both colorimetric assays and compared with those obtained using the British Society for Antimicrobial Chemotherapy reference broth microdilution method. Absolute categorical agreement between the reference and test methods ranged from 79% (cefuroxime) to 100% (vancomycin) for both assays. No minor or major errors occurred using either assay with very major errors ranging from zero (vancomycin) to seven (cefuroxime). Analysis of the distribution of differences in the 1092 dilution MIC results revealed overall agreement, within the accuracy limits of the standard test ( 1 1092 dilution), using the XTT and WST-8 assays of 98% and 88%, respectively. Further studies on 31 ESBL-producing isolates were performed using the XTT method with absolute categorical agreement ranging from 87% (nitrofurantoin) to 100% (ofloxacin and meropenem). No errors were noted for either ofloxacin or meropenem with overall agreement of 91%. The data suggests that XTT is more reliable and accurate than WST-8 for use in a rapid antimicrobial susceptibility test. (c) 2007 Elsevier B.V. All rights reserved.
Resumo:
The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.
Resumo:
In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.
Resumo:
In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.