Ultracompact Retrodirective Antenna Arrays With Superdirective Radiation Patterns

It is shown that the direction-of-arrival (DoA) information carried by an incident electromagnetic (EM) wave can be encoded into the evanescent near field of an electrically small resonance antenna array with a spatial rate higher than that of the incident field oscillation rate in free space. Phase conjugation of the received signal leads to the retrodirection of the near field in the antenna array environment, which in turn generates a retrodirected far-field beam toward the original DoA. This EM phenomenon enables electrically small retrodirective antenna arrays with superdirective, angular super-resolution, auto-pointing properties for an arbitrary DoA. A theoretical explanation of the phenomenon based on first principal observations is given and full-wave simulations demonstrate a realizability route for the proposed retrodirective terminal that is comprised of resonance dipole antenna elements. Specifically, it is shown that a three-element disk-loaded retrodirective dipole array with 0.15\lambda spacings can achieve a 3.4-dBi maximal gain, 3-dBi front-to-back ratio, and 13% return loss fractional bandwidth (at the 10-dB level). Then, it is demonstrated that the radiation gain of a three-element array can be improved to approximately 6 dBi at the expense of the return loss fractional bandwidth reduction (2%).

A Synthesis-free Directional Modulation Transmitter using Retrodirective Array

By modification of the classical retrodirective arrays (RDAs) architecture a directional modulation (DM) transmitter can be realized without the need for synthesis. Importantly, through analytical analysis and exemplar simulations, it is proved that, besides the conventional DM application scenario, i.e., secure transmission to one legitimate receiver located along one spatial direction in free space, the proposed synthesis-free DM transmitter should also perform well for systems where there are more than one legitimate receivers positioned along different directions in free space, and where one or more legitimate receivers exist in a multipath environment. None of these have ever been achieved before using synthesis-free DM arrangements.

Multipair massive MIMO full-duplex relaying with MRC/MRT processing

We consider a multipair relay channel, where multiple sources communicate with multiple destinations with the help of a full-duplex (FD) relay station (RS). All sources and destinations have a single antenna, while the RS is equipped with massive arrays. We assume that the RS estimates the channels by using training sequences transmitted from sources and destinations. Then, it uses maximum-ratio combining/maximum-ratio transmission (MRC/MRT) to process the signals. To significantly reduce the loop interference (LI) effect, we propose two massive MIMO processing techniques: i) using a massive receive antenna array; or ii) using a massive transmit antenna array together with very low transmit power at the RS. We derive an exact achievable rate in closed-form and evaluate the system spectral efficiency. We show that, by doubling the number of antennas at the RS, the transmit power of each source and of the RS can be reduced by 1.5 dB if the pilot power is equal to the signal power and by 3 dB if the pilot power is kept fixed, while maintaining a given quality-of-service. Furthermore, we compare FD and half-duplex (HD) modes and show that FD improves significantly the performance when the LI level is low.

FPGA-based soft-core processors for image processing applications

With security and surveillance, there is an increasing need to process image data efficiently and effectively either at source or in a large data network. Whilst a Field-Programmable Gate Array (FPGA) has been seen as a key technology for enabling this, the design process has been viewed as problematic in terms of the time and effort needed for implementation and verification. The work here proposes a different approach of using optimized FPGA-based soft-core processors which allows the user to exploit the task and data level parallelism to achieve the quality of dedicated FPGA implementations whilst reducing design time. The paper also reports some preliminary
progress on the design flow to program the structure. An implementation for a Histogram of Gradients algorithm is also reported which shows that a performance of 328 fps can be achieved with this design approach, whilst avoiding the long design time, verification and debugging steps associated with conventional FPGA implementations.