LPCVD of tungsten by selective deposition on silicon

Beta-phase W, selectively grown at 440C had resistivity 20 micro-ohm cm and maximum layer thickness 100nm. Hydrogen passivation proved essential in this process. Higher deposition temperatures resulted in increased layer thickness but incorporated WSi2 and alpha- phase W. Self limiting W grown on polycrystalline and heavily doped silicon yielded reduced thickness. Boron is involved in the WF6 reduction reaction but phosphorus is not and becomes incorporated in the W layer. The paper establishes an optimised and novel CVD process suited to IC contact technology. A funded technology transfer contract with National Semiconductor Greenock (M Fallon) resulted from this work.

Material effects on stress-induced defect generation in trenched silicon-on-insulator structures

We have investigated the influence of the material properties of the silicon device layer on the generation of defects, and in particular slip dislocations, in trenched and refilled fusion-bonded silicon-on-insulator structures. A strong dependence of the ease of slip generation on the type of dopant species was observed, with the samples falling into three basic categories; heavily boron-doped silicon showed ready slip generation, arsenic and antimony-doped material was fairly resistant to slip, while silicon moderately or lightly doped with phosphorous or boron gave intermediate behavior. The observed behavior appears to be controlled by differences in the dislocation generation mechanism rather than by dislocation mobility. The introduction of an implanted buried layer at the bonding interface was found to result in an increase in slip generation in the silicon, again with a variation according to the dopant species. Here, the greatest slip occurred for both boron and antimony-implanted samples. The weakening of the implanted material may be related to the presence of a band of precipitates observed in the silicon near the bonding interface. (C) 2001 The Electrochemical Society.

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a midgap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal, gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P+/N+ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET. (C) 2004 Elsevier Ltd. All rights reserved.

Ferroelectricity in Si-doped HfO2 Revealed: A Binary Lead-free Ferroelectric

Static domain structures and polarization dynamics of silicon doped HfO2 are explored. The evolution of ferroelectricity as a function of Si-doping level driving the transition from paraelectricity via ferroelectricity to antiferroelectricity is investigated. Ferroelectric and antiferroelectric properties can be observed locally on the pristine, poled and electroded surfaces, providing conclusive evidence to intrinsic ferroic behavior.