60 resultados para Intellectual Disciplines


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Developed countries, led by the EU and the US, have consistently called for ‘deeper integration’ over the course of the past three decades i.e., the convergence of ‘behind-the-border’ or domestic polices and rules such as services, competition, public procurement, intellectual property (“IP”) and so forth. Following the collapse of the Doha Development Round, the EU and the US have pursued this push for deeper integration by entering into deep and comprehensive free trade agreements (“DCFTAs”) that are comprehensive insofar as they are not limited to tariffs but extend to regulatory trade barriers. More recently, the EU and the US launched negotiations on a Transatlantic Trade and Investment Partnership (“TTIP”) and a Trade in Services Agreement (“TISA”), which put tackling barriers resulting from divergences in domestic regulation in the area of services at the very top of the agenda. Should these agreements come to pass, they may well set the template for the rules of international trade and define the core features of domestic services market regulation. This article examines the regulatory disciplines in the area of services included in existing EU and US DCFTAs from a comparative perspective in order to delineate possible similarities and divergences and assess the extent to which these DCFTAs can shed some light into the possible outcome and limitations of future trade negotiations in services. It also discusses the potential impact of such negotiations on developing countries and, more generally, on the multilateral process.

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A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

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Recent thinking on open innovation and the knowledge-based economy have stressed the importance of external knowledge sources in stimulating innovation. Policy-makers have recognised this, establishing publicly funded Centres of R&D Excellence with the objective of stimulating industry–science links and localised innovation spillovers. Here, we examine the contrasting IP management practices of a group of 18 university- and company-based R&D centres supported by the same regional programme. Our analysis covers all but one of the Centres supported by the programme and suggests marked contrasts between the IP strategies of the university-based and company-based centres. This suggests the potential for very different types of knowledge spillovers from publicly funded R&D centres based in different types of organisations, and a range of alternative policy approaches to the future funding of R&D centres depending on policy-makers’ objectives.