4 resultados para HIGH-TEMPERATURE SYNTHESIS
Resumo:
This letter attempts to comment on an article by dos Reis et al., in the aspects of creep considerationand chemical analysis in maraging steels.
Resumo:
The aim of this study is to clarify if the assumption of ionization equilibrium and a Maxwellian electron energy distribution is valid in flaring solar plasmas. We analyze the 2014 December 20 X1.8 flare, in which the \ion{Fe}{xxi} 187~\AA, \ion{Fe}{xxii} 253~\AA, \ion{Fe}{xxiii} 263~\AA\ and \ion{Fe}{xxiv} 255~\AA\ emission lines were simultaneously observed by the EUV Imaging Spectrometer onboard the Hinode satellite. Intensity ratios among these high temperature Fe lines are compared and departures from isothermal conditions and ionization equilibrium examined. Temperatures derived from intensity ratios involving these four lines show significant discrepancies at the flare footpoints in the impulsive phase, and at the looptop in the gradual phase. Among these, the temperature derived from the \ion{Fe}{xxii}/\ion{Fe}{xxiv} intensity ratio is the lowest, which cannot be explained if we assume a Maxwellian electron distribution and ionization equilibrium, even in the case of a multi-thermal structure. This result suggests that the assumption of ionization equilibrium and/or a Maxwellian electron energy distribution can be violated in evaporating solar plasma around 10MK.
Resumo:
Field-programmable gate arrays are ideal hosts to custom accelerators for signal, image, and data processing but de- mand manual register transfer level design if high performance and low cost are desired. High-level synthesis reduces this design burden but requires manual design of complex on-chip and off-chip memory architectures, a major limitation in applications such as video processing. This paper presents an approach to resolve this shortcoming. A constructive process is described that can derive such accelerators, including on- and off-chip memory storage from a C description such that a user-defined throughput constraint is met. By employing a novel statement-oriented approach, dataflow intermediate models are derived and used to support simple ap- proaches for on-/off-chip buffer partitioning, derivation of custom on-chip memory hierarchies and architecture transformation to ensure user-defined throughput constraints are met with minimum cost. When applied to accelerators for full search motion estima- tion, matrix multiplication, Sobel edge detection, and fast Fourier transform, it is shown how real-time performance up to an order of magnitude in advance of existing commercial HLS tools is enabled whilst including all requisite memory infrastructure. Further, op- timizations are presented that reduce the on-chip buffer capacity and physical resource cost by up to 96% and 75%, respectively, whilst maintaining real-time performance.
Resumo:
Experimental tests have been completed for high-strength 8.8 bolts for studying their mechanical performance subjected to tensile loading. As observed from these tests, failure of structural bolts has been identified as in one of two ways: threads stripping and necking of the threaded portion of the bolt shank, which is possibly due to the degree of fit between internal and external threads. Following the experimental work, a numerical approach has been developed for demonstration of the tensile performance with proper consideration of tolerance class between bolts and nuts. The degree of fit between internal and external threads has been identified as a critical factor affecting failure mechanisms of high-strength structural bolts in tension, which is caused by the machining process. In addition, different constitutive material laws have been taken into account in the numerical simulation, demonstrating the entire failure mechanism for structural bolts with different tolerance classes in their threads. It is also observed that the bolt capacities are closely associated with their failure mechanisms.