Chip design for high-performance DSP

Advances in silicon technology have been a key development in the realisation of many telecommunication and signal processing systems. In many cases, the development of application-specific digital signal processing (DSP) chips is the most cost-effective solution and provides the highest performance. Advances made in computer-aided design (CAD) tools and design methodologies now allow designers to develop complex chips within months or even weeks. This paper gives an insight into the challenges and design methodologies of implementing advanced highperformance chips for DSP. In particular, the paper reviews some of the techniques used to develop circuit architectures from high-level descriptions and the tools which are then used to realise silicon layout.

An Analytical Study of Surplus Value using a Value Driven Design Methodology

People are now becoming more environmentally aware and as a consequence of this, industries such as the aviation industry are striving to design more environmentally friendly products. To achieve this, the current design methodologies must be modified to ensure these issues are considered from product conception through to disposal. This paper discusses the environmental problems in relation to the aviation industry and highlights some logic for making the change from the traditional Systems Engineering approach to the recent design paradigm known as Value Driven Design. Preliminary studies have been undertaken to aid in the understanding of this methodology and the existing surplus value objective function. The main results from the work demonstrate that surplus value works well bringing disparate issues such as manufacture and green taxes together to aid decision making. Further, to date studies on surplus value have used simple sensitivity analysis, but deeper consideration shows non-linear interactions between some of the variables and further work will be needed to fully account for complex issues such as environmental impact and taxes.

Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms

The emergence of programmable logic devices as processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimization of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working implementation on a heterogeneous multiprocessor/field programmable gate array platform, or a standalone system on programmable chip solution. Two particular focuses for Abhainn are the automated but configurable realisation of inter-processor communuication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimization. This paper outlines the approaches employed in both these particular instances.

Holistic Design Strategy for High-Selectivity Low-Loss Integrated Millimetre-Wave Image-Reject Filters

To alleviate practical limitations in the design of mm-wave on-chip image-reject filters, systematic design methodologies are presented. Three low-order filters with high-selectivity and low-loss characteristics are designed and compared. Transmission zeroes are created by means of a quarter-wave transmission line (filter 1) and a series LC resonator (filters 2 and 3). Implemented on SiGe, the filters occupy 0.125, 0.064, and 0.079 mm2 chip area including pads. The measured transmission
losses across 81-86 GHz E-Band frequency range are 3.6-5.2 dB for filter 1, 3.1-4.7 dB for filter 2 and 3.6-5 dB for filter 3 where rejection levels at the image band are greater than 30 dB.

Semi-formal Models to Support Program Development: Autonomic Management within Component Based Parallel and Distributed Programming

Functional and non-functional concerns require different programming effort, different techniques and different methodologies when attempting to program efficient parallel/distributed applications. In this work we present a "programmer oriented" methodology based on formal tools that permits reasoning about parallel/distributed program development and refinement. The proposed methodology is semi-formal in that it does not require the exploitation of highly formal tools and techniques, while providing a palatable and effective support to programmers developing parallel/distributed applications, in particular when handling non-functional concerns.

Memory-Centric Hardware Synthesis from Dataflow Models

Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues in terms of memory organisation and accesses when developing systems from these high level representations. Using a template matching design study, challenges such as modelling memory reuse and minimising buffer requirements are examined, yielding results with significantly less memory requirements and costly off-chip memory accesses.

SoC memory hierarchy derivation from dataflow graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.

QCA Systolic array design

Quantum-dot Cellular Automata (QCA) technology is a promising potential alternative to CMOS technology. To explore the characteristics of QCA and suitable design methodologies, digital circuit design approaches have been investigated. Due to the inherent wire delay in QCA, pipelined architectures appear to be a particularly suitable design technique. Also, because of the pipeline nature of QCA technology, it is not suitable for complicated control system design. Systolic arrays take advantage of pipelining, parallelism and simple local control. Therefore, an investigation into these architectures in QCA technology is provided in this paper. Two case studies, (a matrix multiplier and a Galois Field multiplier) are designed and analyzed based on both multilayer and coplanar crossings. The performance of these two types of interconnections are compared and it is found that even though coplanar crossings are currently more practical, they tend to occupy a larger design area and incur slightly more delay. A general semi-conductor QCA systolic array design methodology is also proposed. It is found that by applying a systolic array structure in QCA design, significant benefits can be achieved particularly with large systolic arrays, even more so than when applied in CMOS-based technology.

An Autopilot Based on a Local Control Network Design for an Unmanned Surface Vehicle

Over recent years, a number of marine autopilots designed using linear techniques have underperformed owing to their inability to cope with nonlinear vessel dynamics. To this end, a new design framework for the development of nonlinear autopilots is proposed herein. Local control networks (LCNs) can be used in the design of nonlinear control systems. In this paper, a LCN approach is taken in the design of a nonlinear autopilot for controlling the nonlinear yaw dynamics of an unmanned surface vehicle known as Springer. It is considered the approach is the first of its kind to be used in marine control systems design. Simulation results are presented and the performance of the nonlinear autopilot is compared with that of an existing Springer linear quadratic Gaussian (LQG) autopilot using standard system performance criteria. From the results it can be concluded the LCN autopilot out performed that based on LQG techniques in terms of the selected criteria. Also it provided more energy saving control strategies and would thereby increase operational duration times for the vehicle during real-time missions.

Rapid design of a single chip adaptive beamformer

This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realize the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilization of a library of parameterizable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.

Sustainability Enhancement of a Turbine Vane Manufacturing Cell through Digital Simulation based Design

Modern manufacturing systems should satisfy emerging needs related to sustainable development. The design of sustainable manufacturing systems can be valuably supported by simulation, traditionally employed mainly for time and cost reduction. In this paper, a multi-purpose digital simulation approach is proposed to deal with sustainable manufacturing systems design through Discrete Event Simulation (DES) and 3D digital human modelling. DES models integrated with data on power consumption of the manufacturing equipment are utilized to simulate different scenarios with the aim to improve productivity as well as energy efficiency, avoiding resource and energy waste. 3D simulation based on digital human modelling is employed to assess human factors issues related to ergonomics and safety of manufacturing systems. The approach is implemented for the sustainability enhancement of a real manufacturing cell of the aerospace industry, automated by robotic deburring. Alternative scenarios are proposed and simulated, obtaining a significant improvement in terms of energy efficiency (−87%) for the new deburring cell, and a reduction of energy consumption around −69% for the coordinate measuring machine, with high potential annual energy cost savings and increased energy efficiency. Moreover, the simulation-based ergonomic assessment of human operator postures allows 25% improvement of the workcell ergonomic index.