5 resultados para First delay


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This letter investigates the optimum decision delay and tap-length of the finite-length decision feedback equalizer. First we show that, if the feedback filter (FBF) length N-b is equal to or larger than the channel memory upsilon and the decision delay Delta is smaller than the feedforward filter (FFF) length N-f, then only the first Delta + 1 elements of the FFF can be nonzero. Based on this result we prove that the maximum effective FBF length is equal to the channel memory upsilon, and if N-b greater than or equal to upsilon and N-f is long enough, the optimum decision delay that minimizes the MMSE is N-f - 1.

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Objective: A history of childhood trauma is common in individuals who later develop psychosis. Similar neuroanatomical abnormalities are observed in people who have been exposed to childhood trauma and people with psychosis. However, the relationship between childhood trauma and such abnormalities in psychosis has not been investigated. This study aimed to explore the association between the experience of childhood trauma and hippocampal and amygdalar volumes in a first-episode psychosis (FEP) population. Methods: The study employed an observational retrospective design. Twenty-one individuals, who had previously undergone magnetic resonance imaging procedures as part of the longitudinal Northern Ireland First-Episode Psychosis Study, completed measures assessing traumatic experiences and were included in the analysis. Data were subject to correlation analyses (rand rob). Potential confounding variables (age at FEP and delay to scan from recruitment) were selected a priori for inclusion in multiple regression analyses. Results: There was a high prevalence of lifetime (95%) and childhood (76%) trauma in the sample. The experience of childhood trauma was a significant predictor of left hippocampal volume, although age at FEP also significantly contributed to this model. There was no significant association between predictor variables and right hippocampal volume. The experience of childhood trauma was a significant predictor of right and total amygdalar volumes and the hippocampal/amygdalar complex volume as a whole. Conclusions: The findings indicate that childhood trauma is associated with neuroanatomical measures in FEP. Future research controlling for childhood traumatic experiences may contribute to explaining brain morphology in people with psychosis.

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Side-channel attacks (SCA) threaten electronic cryptographic devices and can be carried out by monitoring the physical characteristics of security circuits. Differential Power Analysis (DPA) is one the most widely studied side-channel attacks. Numerous countermeasure techniques, such as Random Delay Insertion (RDI), have been proposed to reduce the risk of DPA attacks against cryptographic devices. The RDI technique was first proposed for microprocessors but it was shown to be unsuccessful when implemented on smartcards as it was vulnerable to a variant of the DPA attack known as the Sliding-Window DPA attack.Previous research by the authors investigated the use of the RDI countermeasure for Field Programmable Gate Array (FPGA) based cryptographic devices. A split-RDI technique wasproposed to improve the security of the RDI countermeasure. A set of critical parameters wasalso proposed that could be utilized in the design stage to optimize a security algorithm designwith RDI in terms of area, speed and power. The authors also showed that RDI is an efficientcountermeasure technique on FPGA in comparison to other countermeasures.In this article, a new RDI logic design is proposed that can be used to cost-efficiently implementRDI on FPGA devices. Sliding-Window DPA and realignment attacks, which were shown to beeffective against RDI implemented on smartcard devices, are performed on the improved RDIFPGA implementation. We demonstrate that these attacks are unsuccessful and we also proposea realignment technique that can be used to demonstrate the weakness of RDI implementations.

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Burkholderia cenocepacia is an opportunistic pathogen causing serious infections in patients with cystic fibrosis. The widespread distribution of this bacterium in the environment suggests that it must adapt to stress to be able to survive. We identified in B. cenocepacia K56-2 a gene predicted to encode RpoE, the extra-cytoplasmic stress response regulator. The rpoE gene is the first gene of a predicted operon encoding proteins homologous to RseA, RseB, MucD and a protein of unknown function. The genomic organization and the co-transcription of these genes were confirmed by PCR and RT-PCR. The mucD and rpoE genes were mutated, giving rise to B. cenocepacia RSF24 and RSF25, respectively. While mutant RSF24 did not demonstrate any growth defects under the conditions tested, RSF25 was compromised for growth under temperature (44 degrees C) and osmotic stress (426 mM NaCl). Expression of RpoE in trans could complement the osmotic growth defect but exacerbated temperature sensitivity in both RSF25 and wild-type K56-2. Inactivation of rpoE altered the bacterial cell surface, as indicated by increased binding of the fluorescent dye calcofluor white and by an altered outer-membrane protein profile. These cell surface changes were restored by complementation with a plasmid encoding rpoE. Macrophage infections in which bacterial colocalization with fluorescent dextran was examined demonstrated that the rpoE mutant could not delay the fusion of B. cenocepacia-containing vacuoles with lysosomes, in contrast to the parental strain K56-2. These data show that B. cenocepacia rpoE is required for bacterial growth under certain stress conditions and for the ability of intracellular bacteria to delay phagolysosomal fusion in macrophages.

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Quantum-dot cellular automata (QCA) is potentially a very attractive alternative to CMOS for future digital designs. Circuit designs in QCA have been extensively studied. However, how to properly evaluate the QCA circuits has not been carefully considered. To date, metrics and area-delay cost functions directly mapped from CMOS technology have been used to compare QCA designs, which is inappropriate due to the differences between these two technologies. In this paper, several cost metrics specifically aimed at QCA circuits are studied. It is found that delay, the number of QCA logic gates, and the number and type of crossovers, are important metrics that should be considered when comparing QCA designs. A family of new cost functions for QCA circuits is proposed. As fundamental components in QCA computing arithmetic, QCA adders are reviewed and evaluated with the proposed cost functions. By taking the new cost metrics into account, previous best adders become unattractive and it has been shown that different optimization goals lead to different “best” adders.