64-point Fourier transform chip for digital television applications

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

Reciprocal value propositions in practice: Constraints in digital markets

The value proposition concept, while forming a central foundational premise of service-dominant (S-D) logic, has nevertheless been treated somewhat ambiguously. Recent work in attempting to address this has focused through a S-D logic lens on the reciprocal nature of value propositions. Important to this work has been a focus on communicative interactions and resource integration between network suppliers and customers. Overall, value proposition thinking has not studied in detail their adoption and use in practice. Considering the compelling notion of reciprocity, there have been recent calls for research to consider reciprocal value propositions in practice. The overall aim of this paper, therefore, was to explore how reciprocal value propositions are developed (or not) in practice at the network level. The study was set in the mobile television (TV) sector, which, as an internet-driven sector, is viewed as particularly pertinent. To conduct the study an S-D logic and Industrial Marketing and Purchasing (IMP) Group framework are integrated for the first time. A key finding is that while the reciprocal value proposition concept is theoretically intuitive, it is by no means inevitable in practice. Reciprocal value propositions were found to be simultaneously constrained, and, potentially enabled by these constraints in practice. At an overall level this paper contributes to the ongoing collaborative process, which aims to move S-D logic from a framework to a theory. More specifically, we provide new insights into the development of reciprocal value propositions in practice.