Energy storage in electrochemical capacitors: designing functional materials to improve device performance

Electrochemical capacitors, also known as supercapacitors, are becoming increasingly important components in energy storage, although their widespread use has not been attained due to a high cost/ performance ratio. Fundamental research is contributing to lowered costs through the engineering of new materials. Currently the most viable materials used in electrochemical capacitors are biomassderived and polymer-derived activated carbons, although other carbon materials are useful research tools. Metal oxides could result in a step change for electrochemical capacitor technology and is an exciting area of research. The selection of an appropriate electrolyte and electrode structure is fundamental in determining device performance. Although there are still many uncertainties in understanding the underlying mechanisms involved in electrochemical capacitors, genuine progress continues to be made. It is argued that a large, collaborative international research programme is necessary to fully develop the potential of electrochemical capacitors.

Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

Electrical Characterisation of SOI Substrates Incorporating WSix Ground Planes

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of similar to 0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.

SiGe HBTs on Bonded SOI Incorporating Buried Silicide Layers

The performance of silicon bipolar transistors has been significantly improved by the use of ultra narrow base layers of SiGe. To further improve device performance by minimising parasitic resistance and capacitance the authors produced an unique silicon-on-insulator (SOI) substrate incorporating a buried tungsten disilicide layer. This structure forms the basis of a recent submission by Zarlink Semiconductors ( Silvaco, DeMontfort & Queen�s) to DTI for high voltage devices for automotive applications. The Queen�s part of the original EPSRC project was rated as tending to outstanding.

A probabilistic modelling scheme for analysis of long-term failure of cemented femoral joint replacements

Reliable prediction of long-term medical device performance using computer simulation requires consideration of variability in surgical procedure, as well as patient-specific factors. However, even deterministic simulation of long-term failure processes for such devices is time and resource consuming so that including variability can lead to excessive time to achieve useful predictions. This study investigates the use of an accelerated probabilistic framework for predicting the likely performance envelope of a device and applies it to femoral prosthesis loosening in cemented hip arthroplasty.
A creep and fatigue damage failure model for bone cement, in conjunction with an interfacial fatigue model for the implant–cement interface, was used to simulate loosening of a prosthesis within a cement mantle. A deterministic set of trial simulations was used to account for variability of a set of surgical and patient factors, and a response surface method was used to perform and accelerate a Monte Carlo simulation to achieve an estimate of the likely range of prosthesis loosening. The proposed framework was used to conceptually investigate the influence of prosthesis selection and surgical placement on prosthesis migration.
Results demonstrate that the response surface method is capable of dramatically reducing the time to achieve convergence in mean and variance of predicted response variables. A critical requirement for realistic predictions is the size and quality of the initial training dataset used to generate the response surface and further work is required to determine the recommendations for a minimum number of initial trials. Results of this conceptual application predicted that loosening was sensitive to the implant size and femoral width. Furthermore, different rankings of implant performance were predicted when only individual simulations (e.g. an average condition) were used to rank implants, compared with when stochastic simulations were used. In conclusion, the proposed framework provides a viable approach to predicting realistic ranges of loosening behaviour for orthopaedic implants in reduced timeframes compared with conventional Monte Carlo simulations.

The hydrodynamics of small seabed mounted bottom hinged wave energy converters in shallow water:PhD thesis

This thesis investigates the hydrodynamics of a small, seabed mounted, bottom hinged, wave energy converter in shallow water. The Oscillating Wave Surge Converter is a pitching flap-type device which is located in 10-15m of water to take advantage of the amplification of horizontal water particle motion in shallow water. A conceptual model of the hydrodynamics of the device has been formulated and shows that, as the motion of the flap is highly constrained, the magnitude of the force applied to the flap by the wave is strongly linked to the power absorption.

An extensive set of experiments has been carried out in the wave tank at Queen’s University at both 40th and 20th scales. The experiments have included testing in realistic sea states to estimate device performance as well as fundamental tests using small amplitude monochromatic waves to determine the force applied to the flap by the waves. The results from the physical modelling programme have been used in conjunction with numerical data from WAMIT to validate the conceptual model.

The work finds that tuning the OWSC to the incident wave periods is problematic and only results in a marginal increase in power capture. It is also found that the addition of larger diameter rounds to the edges of the flap reduces viscous losses and has a greater effect on the performance of the device than tuning. As wave force is the primary driver of device performance it is shown that the flap should fill the water column and should pierce the water surface to reduce losses due to wave overtopping.

With the water depth fixed at approximately 10m it is shown that the width of the flap has the greatest impact on the magnitude of wave force, and thus device performance. An 18m wide flap is shown to have twice the absorption efficiency of a 6m wide flap and captures 6 times the power. However, the increase in power capture with device width is not limitless and a 24m wide flap is found to be affected by two-dimensional hydrodynamics which reduces its performance per unit width, especially in sea states with short periods. It is also shown that as the width increases the performance gains associated with the addition of the end effectors reduces. Furthermore, it is shown that as the flap width increases the natural pitching period of the flap increases, thus detuning the flap further from the wave periods of interest for wave energy conversion.

The effect of waves approaching the flap from an oblique angle is also investigated and the power capture is found to decrease with the cosine squared of the encounter angle. The characteristic of the damping applied by the power take off system is found to have a significant effect on the power capture of the device, with constant damping producing between 20% and 30% less power than quadratic damping. Furthermore, it is found that applying a higher level of damping, or a damping bias, to the flap as it pitches towards the beach increases the power capture by 10%.

A further set of experiments has been undertaken in a case study used to predict the power capture of a prototype of the OWSC concept. The device, called the Oyster Demonstrator, has been developed by Aquamarine Power Ltd. and is to be installed at the European Marine Energy Centre, Scotland, in 2009.

The work concludes that OWSC is a viable wave energy converter and absorption efficiencies of up 75% have been measured. It is found that to maximise power absorption the flap should be approximately 20m wide with large diameter rounded edges, having its pivot close to the seabed and its top edge piercing the water surface.

Wave Interaction with an Oscillating Wave Surge Converter, Part 1: Viscous Effects

Bottom hinged oscillating wave surge converters are known to be an efficient method of extracting power from ocean waves. The present work deals with experimental and numerical studies of wave interactions with an oscillating wave surge converter. It focuses on two aspects: (1) viscous effects on device performance under normal operating conditions; and (2) effects of slamming on device survivability under extreme conditions. Part I deals with the viscous effects while the extreme sea conditions will be presented in Part II. The numerical simulations are performed using the commercial CFD package ANSYS FLUENT. The comparison between numerical results and experimental measurements shows excellent agreement in terms of capturing local features of the flow as well as the dynamics of the device. A series of simulations is conducted with various wave conditions, flap configurations and model scales to investigate the viscous and scaling effects on the device. It is found that the diffraction/radiation effects dominate the device motion and that the viscous effects are negligible for wide flaps.

Designing Short Term Wave Traces to Assess Wave Power Devices

In recent years modern numerical methods have been employed in the design of Wave Energy Converters (WECs), however the high computational costs associated with their use makes it prohibitive to undertake simulations involving statistically relevant numbers of wave cycles. Experimental tests in wave tanks could also be performed more efficiently and economically if short time traces, consisting of only a few wave cycles, could be used to evaluate the hydrodynamic characteristics of a particular device or design modification. Ideally, accurate estimations of device performance could be made utilizing results obtained from investigations with a relatively small number of wave cycles. However the difficulty here is that many WECs, such as the Oscillating Wave Surge Converter (OWSC), exhibit significant non-linearity in their response. Thus it is challenging to make accurate predictions of annual energy yield for a given spectral sea state using short duration realisations of that sea. This is because the non-linear device response to particular phase couplings of sinusoidal components within those time traces might influence the estimate of mean power capture obtained. As a result it is generally accepted that the most appropriate estimate of mean power capture for a sea state be obtained over many hundreds (or thousands) of wave cycles. This ensures that the potential influence of phase locking is negligible in comparison to the predictions made. In this paper, potential methods of providing reasonable estimates of relative variations in device performance using short duration sea states are introduced. The aim of the work is to establish the shortness of sea state required to provide statistically significant estimations of the mean power capture of a particular type of Wave Energy Converter. The results show that carefully selected wave traces can be used to reliably assess variations in power output due to changes in the hydrodynamic design or wave climate. 

Ultrafast charge-transfer in organic photovoltaic interfaces: geometrical and functionalization effects

Understanding the microscopic mechanisms of electronic excitation in organic photovoltaic cells is a challenging problem in the design of efficient devices capable of performing sunlight harvesting. Here we develop and apply an ab initio approach based on time-dependent density functional theory and Ehrenfest dynamics to investigate photoinduced charge transfer in small organic molecules. Our calculations include mixed quantum–classical dynamics with ions moving classically and electrons quantum mechanically, where no experimental external parameter other than the material geometry is required. We show that the behavior of photocarriers in zinc phthalocyanine (ZnPc) and C60 systems, an effective prototype system for organic solar cells, is sensitive to the atomic orientation of the donor and the acceptor units as well as the functionalization of covalent molecules at the interface. In particular, configurations with the ZnPc molecules facing on C60 facilitate charge transfer between substrate and molecules that occurs within 200 fs. In contrast, configurations where ZnPc is tilted above C60 present extremely low carrier injection efficiency even at longer times as an effect of the larger interfacial potential level offset and higher energetic barrier between the donor and acceptor molecules. An enhancement of charge injection into C60 at shorter times is observed as binding groups connect ZnPc and C60 in a dyad system. Our results demonstrate a promising way of designing and controlling photoinduced charge transfer on the atomic level in organic devices that would lead to efficient carrier separation and maximize device performance.

Analysis and Synthesis of pHEMT Class-E Amplifiers with Shunt Inductor including ON-State Active-Device Resistance Effects

In this theoretical paper, the analysis of the effect that ON-state active-device resistance has on the performance of a Class-E tuned power amplifier using a shunt inductor topology is presented. The work is focused on the relatively unexplored area of design facilitation of Class-E tuned amplifiers where intrinsically low-output-capacitance monolithic microwave integrated circuit switching devices such as pseudomorphic high electron mobility transistors are used. In the paper, the switching voltage and current waveforms in the presence of ON-resistance are analyzed in order to provide insight into circuit properties such as RF output power, drain efficiency, and power-output capability. For a given amplifier specification, a design procedure is illustrated whereby it is possible to compute optimal circuit component values which account for prescribed switch resistance loss. Furthermore, insight into how ON-resistance affects transistor selection in terms of peak switch voltage and current requirements is described. Finally, a design example is given in order to validate the theoretical analysis against numerical simulation.

Hardware Performance Analysis of the SHACAL-2 Encryption Algorithm

A hardware performance analysis of the SHACAL-2 encryption algorithm is presented in this paper. SHACAL-2 was one of four symmetric key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative in 2003. The paper describes a fully pipelined encryption SHACAL-2 architecture implemented on a Xilinx Field Programmable Gate Array (FPGA) device that achieves a throughput of over 25 Gbps. This is the fastest private key encryption algorithm architecture currently available. The SHACAL-2 decryption algorithm is also defined in the paper as it was not provided in the NESSIE submission.

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.