Optimisation of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG SOI MOSFETs with high- k gate dielectrics

Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a midgap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal, gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P+/N+ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET. (C) 2004 Elsevier Ltd. All rights reserved.

Upper and lower bounds of 180 degrees unit element of a ridge waveguide: Calculations and measurements

The upper and lower bounds on the actual solution of any microwave structure is of general interest. The purpose of this letter is to compare some calculations using the mode-matching and finite-element methods, with some measurements on a 180 degrees ridge waveguide insert between standard WR62 rectangular waveguides. The work suggests that the MMM produces an upper bound, while the FEM places a lower bound on the measurement. (C) 2001 John Wiley & Sons, Inc.