Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

Rapid design of a single chip adaptive beamformer

This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realize the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilization of a library of parameterizable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.

The development of a surface defect machining method for hard turning processes

Hard turning (HT) is a material removal process employing a combination of a single point cutting tool and high speeds to machine hard ferrous alloys which exhibit hardness values over 45 HRC. In this paper, a surface defect machining (SDM) method for HT is proposed which harnesses the combined advantages of porosity machining and pulsed laser pre-treatment processing. From previous experimental work, this was shown to provide better controllability of the process and improved quality of the machined surface. While the experiments showed promising results, a comprehensive understanding of this new technique could only be achieved through a rigorous, in depth theoretical analysis. Therefore, an assessment of the SDM technique was carried out using both finite element method (FEM) and molecular dynamics (MD) simulations.
FEM modelling was used to compare the conventional HT of AISI 4340 steel (52 HRC) using an Al2O3 insert with the proposed SDM method. The simulations showed very good agreement with the previously published experimental results. Compared to conventional HT, SDM provided favourable machining outcomes, such as reduced shear plane angle, reduced average cutting forces, improved surface roughness, lower residual stresses on the machined surface, reduced tool–chip interface contact length and increased chip flow velocity. Furthermore, a scientific explanation of the improved surface finish was revealed using a state-of-the-art MD simulation model which suggested that during SDM, a combination of both the cutting action and rough polishing action help improve the machined surface finish.

Investigation of chip formation and fracture toughness in orthogonal cutting of UD-CFRP

Features of chip formation can inform the mechanism of a machining process. In this paper, a series of orthogonal cutting experiments were carried out on unidirectional carbon fiber reinforced polymer (UD-CFRP) under cutting speed of 0.5 m/min. The specially designed orthogonal cutting tools and high-speed camera were used in this paper. Two main factors are found to influence the chip morphology, namely the depth of cut (DOC) and the fiber orientation (angle 휃), and the latter of which plays a more dominant role. Based on the investigation of chip formation, a new approach is proposed for predicting fracture toughness of the newly machined surface and the total energy consumption during CFRP orthogonal cutting is introduced as a function of the surface energy of machined surface, the energy consumed to overcome friction, and the energy for chip fracture. The results show that the proportion of energy spent on tool-chip friction is the greatest, and the proportions of energy spent on creating new surface decrease with the increasing of fiber angle.