9 resultados para BANDWIDTH HUNGRY APPLICATIONS
Resumo:
The widespread availability and demand for multimedia capable devices and multimedia content have fueled the need for high-speed wireless connectivity beyond the capabilities of existing commercial standards. While fiber optic data transfer links can provide multigigabit- per-second data rates, cost and deployment are often prohibitive in many applications. Wireless links, on the contrary, can provide a cost-effective fiber alternative to interconnect the outlining areas beyond the reach of the fiber rollout. With this in mind, the ever increasing demand for multi-gigabit wireless applications, fiber segment replacement mobile backhauling and aggregation, and covering the last mile have posed enormous challenges for next generation wireless technologies. In particular, the unbalanced temporal and geographical variations of spectrum usage along with the rapid proliferation of bandwidth- hungry mobile applications, such as video streaming with high definition television (HDTV) and ultra-high definition video (UHDV), have inspired millimeter-wave (mmWave) communications as a promising technology to alleviate the pressure of scarce spectrum resources for fifth generation (5G) mobile broadband.
Resumo:
The future convergence of voice, video and data applications on the Internet requires that next generation technology provides bandwidth and delay guarantees. Current technology trends are moving towards scalable aggregate-based systems where applications are grouped together and guarantees are provided at the aggregate level only. This solution alone is not enough for interactive video applications with sub-second delay bounds. This paper introduces a novel packet marking scheme that controls the end-to-end delay of an individual flow as it traverses a network enabled to supply aggregate- granularity Quality of Service (QoS). IPv6 Hop-by-Hop extension header fields are used to track the packet delay encountered at each network node and autonomous decisions are made on the best queuing strategy to employ. The results of network simulations are presented and it is shown that when the proposed mechanism is employed the requested delay bound is met with a 20% reduction in resource reservation and no packet loss in the network.
Resumo:
In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain along with three times higher cutoff frequency as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle ratio of 3.2 and operated below a bias current of 80 microamps demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology. Index Terms—Analog/RF, double gate, gain-bandwidth product, .
Resumo:
The quality factor of microwave resonators miniaturised by virtue of periodic loading is assessed. Five X-band resonators in E-plane technology with different miniaturisation factors have been designed to resonate at approximately the same frequency. The loaded quality factor is extracted from the fractional bandwidth and subsequently employed to estimate the unloaded quality factor. The study reveals that the unloaded quality factor drops approximately linearly with the miniaturisation. Subsequently design guidelines for E-plane filters with periodically loaded resonators are provided by means of an example involving a fifth-order filter. Full-wave simulated and experimental results are presented to validate the study.
Resumo:
A Digital Video Broadcast Terrestrial (DVB-T) based passive radar requires the development of an antenna array that performs satisfactorily over the entire DVB-T band. The array should require no mechanical adjustments to inter-element spacing to correspond to the DVB-T carrier frequency used for any particular measurement. This paper will describe the challenges involved in designing an antenna array with a bandwidth of 450 MHz. It will discuss the design procedure and demonstrate a number of simulated array configurations. The final configuration of the array will be shown as well as simulations of the expected performance over the desired frequency span.
Resumo:
Smart Grids are characterized by the application of information communication technology (ICT) to solve electrical energy challenges. Electric power networks span large geographical areas, thus a necessary component of many Smart Grid applications is a wide area network (WAN). For the Smart Grid to be successful, utilities must be confident that the communications infrastructure is secure. This paper describes how a WAN can be deployed using WiMAX radio technology to provide high bandwidth communications to areas not commonly served by utility communications, such as generators embedded in the distribution network. A planning exercise is described, using Northern Ireland as a case study. The suitability of the technology for real-time applications is assessed using experimentally obtained latency data.
Resumo:
Software-programmable `soft' processors have shown tremendous potential for efficient realisation of high performance signal processing operations on Field Programmable Gate Array (FPGA), whilst lowering the design burden by avoiding the need to design fine-grained custom circuit archi-tectures. However, the complex data access patterns, high memory bandwidth and computational requirements of sliding window applications, such as Motion Estimation (ME) and Matrix Multiplication (MM), lead to low performance, inefficient soft processor realisations. This paper resolves this issue, showing how by adding support for block data addressing and accelerators for high performance loop execution, performance and resource efficiency over four times better than current best-in-class metrics can be achieved. In addition, it demonstrates the first recorded real-time soft ME estimation realisation for H.263 systems.