A 75-81 GHz, 14.3 dBm Peak Output Power, 21 dB Peak Gain, SiGe Power-Combining Amplifier Operating from a Single 3.3 V Supply

A compact differential 4-way power combiner with 2.3 dB loss and high common-mode rejection characteristic for use in mm-wave PAs is presented. A complete circuit comprised of a power splitter, two-stage cascode PA array, and a power combiner was implemented in SiGe technology. Measured small-signal gain of at least 17 dB was obtained from 74.5 GHz to 80.5 GHz with a peak 21 dB at 79 GHz. The prototype delivered 13.2 dBm P1dB and 14.3 dBm Psat when operated from a single 3.3 V supply at 75 GHz.

Comprehensive numerical modelling of the performance of a second harmonic generation stage coupled with a low-gain optical parametric amplifier

We present a comprehensive model for predicting the full performance of a second harmonic generation-optical parametric amplification system that aims at enhancing the temporal contrast of laser pulses. The model simultaneously takes into account all the main parameters at play in the system such as the group velocity mismatch, the beam divergence, the spectral content, the pump depletion, and the length of the nonlinear crystals. We monitor the influence of the initial parameters of the input pulse and the interdependence of the two related non-linear processes on the performance of the system and show its optimum configuration. The influence of the initial beam divergence on the spectral and the temporal characteristics of the generated pulse is discussed. In addition, we show that using a crystal slightly longer than the optimum length and introducing small delay between the seed and the pump ensures maximum efficiency and compensates for the spectral shift in the optical parametric amplification stage in case of chirped input pulse. As an example, calculations for bandwidth transform limited and chirped pulses of sub-picosecond duration in beta barium borate crystal are presented.

Inverse Class-E Amplifier With Transmission-Line Harmonic Suppression

This paper reports on the design methodology and experimental characterization of the inverse Class-E power amplifier. A demonstration amplifier with excellent second and third harmonic-suppression levels has been designed, constructed, and measured. The circuit fabricated using a 1.2-min gate-width GaAs MESFET is shown to be able to deliver 22-dBm output power at 2.3 GHz. The amplifier achieves a peak power-added efficiency of 64 % and drain efficiency of 69 %, and exhibits 11.6 dB power gain when operated from a 3-V supply voltage. Comparisons of simulated and measured results are given with good agreement between them being obtained. Experimental results are presented for the amplifier's response to Gaussian minimum shift keying modulation, where a peak error vector modulation value of 0.6% is measured.

2.4 GHz Class-E power amplifier with transmissionline harmonic terminations

The design procedure, fabrication and measurement of a Class-E power amplifier with excellent second- and third-harmonic suppression levels are presented. A simplified design technique offering compact physical layout is proposed. With a 1.2 mm gate-width GaAs MESFET as a switching device, the amplifier is capable of delivering 19.2 dBm output power at 2.41 GHz, achieves peak PAE of 60% and drain efficiency of 69%, and exhibits 9 dB power gain when operated from a 3 V DC supply voltage. When compared to the classical Class-E two-harmonic termination amplifier, the Class-E amplifier employing three-harmonic terminations has more than 10% higher drain efficiency and 23 dB better third-harmonic suppression level. Experimental results are presented and good agreement with simulation is obtained. Further, to verify the practical implementation in communication systems, the Bluetooth-standard GFSK modulated signal is applied to both two- and three-harmonic amplifiers. The measured RMS FSK deviation error and RMS magnitude error were, for the three-harmonic case, 1.01 kHz and 0.122%, respectively, and, for the two-harmonic case, 1.09 kHz and 0.133%. © 2007 The Institution of Engineering and Technology.

Digital Baseband Predistortion Based Linearized Broadband Inverse Class-E Power Amplifier

A newly introduced inverse class-E power amplifier (PA) was designed, simulated, fabricated, and characterized. The PA operated at 2.26 GHz and delivered 20.4-dBm output power with peak drain efficiency (DE) of 65% and power gain of 12 dB. Broadband performance was achieved across a 300-Mitz bandwidth with DE of better than 50% and 1-dB output-power flatness. The concept of enhanced injection predistortion with a capability to selectively suppress unwanted sub-frequency components and hence suitable for memory effects minimization is described coupled with a new technique that facilitates an accurate measurement of the phase of the third-order intermodulation (IM3) products. A robust iterative computational algorithm proposed in this paper dispenses with the need for manual tuning of amplitude and phase of the IM3 injected signals as commonly employed in the previous publications. The constructed inverse class-E PA was subjected to a nonconstant envelope 16 quadrature amplitude modulation signal and was linearized using combined lookup table (LUT) and enhanced injection technique from which superior properties from each technique can be simultaneously adopted. The proposed method resulted in 0.7% measured error vector magnitude (in rms) and 34-dB adjacent channel leakage power ratio improvement, which was 10 dB better than that achieved using the LUT predistortion alone.

Power-Combining Class-E Amplifier With Finite Choke

A recently introduced power-combining scheme for a Class-E amplifier is, for the first time, experimentally validated in this paper. A small value choke of 2.2 nH was used to substitute for the massive dc-feed inductance required in the classic Class-E circuit. The power-combining amplifier presented, which operates from a 3.2-V dc supply voltage, is shown to be able to deliver a 24-dBm output power and a 9.5-dB gain, with 64% drain efficiency and 57% power-added efficiency at 2.4 GHz. The power amplifier exhibits a 350-MHz bandwidth within which a drain efficiency that is better than 60% and an output power that is higher than 22 dBm were measured. In addition, by adopting three-harmonic termination strategy, excellent second-and third-harmonic suppression levels of 50 and 46 dBc, respectively, were obtained. The complete design cycle from analysis through fabrication to characterization is explained. © 2010 IEEE.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.

Non Classical Design in MOSFETs for Improving OTA gain-bandwidth trade off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain along with three times higher cutoff frequency as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle ratio of 3.2 and operated below a bias current of 80 microamps demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology. Index Terms—Analog/RF, double gate, gain-bandwidth product, .

AN INJECTOR AMPLIFIER DOUBLE TARGET CONFIGURATION FOR THE NE-LIKE GE X-RAY LASER SCHEME

The XUV lasing output from one germanium slab target has been efficiently coupled into, and further amplified in, a second plasma produced by irradiation of a similar target from the opposite direction. The operation of such a double target was shown to be strongly dependent on the distance by which the two target surfaces were displaced. The line brightness peaked for a surface displacement of approximately 200-mu-m and it was observed that the pointing direction of one output beam could be controlled by the surface separation in an asymmetric geometry. Gain length products of approximately 16 with estimated output powers close to the megawatt level were achieved on both the 23.2 and 23.6 nm J=2-1 transitions for an optimised target configuration. Maximum effective coupling efficiencies of the individual outputs from double targets, comprising 2.2 and 1.4 cm length components, approached 100% for beams propagating from the shorter to the longer target.

A 76-84 GHz SiGe power amplifier array employing low-loss four-way differential combining transformer

This paper presents holistic design of a novel four-way differential power-combining transformer for use in millimeter-wave power-amplifier (PA). The combiner with an inner radius of 25 µm exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. It is designed to simultaneously act as a balanced-to-unbalanced converter, removing the need for additional BALUNs typically required in differential circuits. A complete circuit comprised of a power splitter, two-stage differential cascode PA array, a power combiner as well as input and output matching elements was designed and realized in SiGe technology with f/f 170/250 GHz. Measured small-signal gain of at least 16.8 dB was obtained from 76.4 to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm output referred 1 dB compression point and 14 dBm saturated output power when operated from a 3.2 V dc supply voltage at 78 GHz.

A SiGe Power Amplifier with Integrated BALUNs for 81-86 GHz E-Band Backhaul Applications

The design of a two-stage differential cascode power amplifier (PA) for 81-86 GHz E-band applications is presented. The PA was realised in SiGe technology with fT/fmax 170/250 GHz. A broadband transformer with efficiency higher than 79.4% from 71 GHz to 96 GHz is used as a BALUN. The PA delivers a 4.5 dBm saturated output power and exhibits a 13.4 dB gain at 83.6 GHz. The input and output return losses agree well with the design specifications.

Full duplex reflection amplifier tag

The authors describe a reflection amplifier adapted to have both a reflection and a transmission port. The amplifier uses a single silicon bipolar transistor and demonstrates a reflection gain of 13 dB, transmission gain of 10 dB and 3.4 dB noise figure at 5.25 GHz. The added feature of transmission gain in the reflection amplifier permits practical implementation of full duplex microwave radiofrequency indentification (RFID) tag operation. By using a simple subcarrier modulation scheme full duplex RFID operation utilising this amplifier is demonstrated. These results indicate that for 27 dBm (0.5 W) effective isotropic radiated power (EIRP) transmit power it should be possible to obtain approximately 8 m downlink range and 25 m uplink range

Low Noise Amplifier With Integrated Balanced Antenna for 60 GHz Wireless Communications

The implementation of a dipole antenna co-designed and monolithically integrated with a low noise amplifier (LNA) on low resistivity Si substrate (20 Omega . cm) manufactured in 0.35 mu m commercial SiGe HBT process with f(T)/f(max) of 170 GHz and 250 GHz is investigated theoretically and experimentally. An air gap is introduced between the chip and a reflective ground plane, leading to substantial improvements in efficiency and gain. Moreover, conjugate matching conditions between the antenna and the LNA are exploited, enhancing power transfer between without any additional matching circuit. A prototype is fabricated and tested to validate the performance. The measured 10-dB gain of the standalone LNA is centered at 58 GHz with a die size of 0.7 mm x 0.6 mm including all pads. The simulated results showed antenna directivity of 5.1 dBi with efficiency higher than 70%. After optimization, the co-designed LNA-Antenna chip with a die size of 3 mm x 2.8 mm was characterized in anechoic chamber environment. A maximum gain of higher than 12 dB was obtained.