A scaling method for modelling the crashworthiness of novel roadside barrier designs

In this paper, a novel method for modelling a scaled vehicle–barrier crash test similar to the 20◦ angled barrier test specified in EN 1317 is reported. The intended application is for proof-of-concept evaluation of novel roadside barrier designs, and as a cost-effective precursor to full-scale testing or detailed computational modelling. The method is based on the combination of the conservation of energy law and the equation of motion of a spring mass system representing the impact, and shows, for the first time, the feasibility of applying classical scaling theories to evaluation of roadside barrier design. The scaling method is used to set the initial velocity of the vehicle in the scaled test and to provide scaling factors to convert the measured vehicle accelerations in the scaled test to predicted full-scale accelerations. These values can then be used to calculate the Acceleration Severity Index score of the barrier for a full-scale test. The theoretical validity of the method is demonstrated by comparison to numerical simulations of scaled and full-scale angled barrier impacts using multibody analysis implemented in the crash simulation software MADYMO. Results show a maximum error of 0.3% ascribable to the scaling method.

A recursive rule base adjustment algorithm for a fuzzy logic controller

This paper introduces a recursive rule base adjustment to enhance the performance of fuzzy logic controllers. Here the fuzzy controller is constructed on the basis of a decision table (DT), relying on membership functions and fuzzy rules that incorporate heuristic knowledge and operator experience. If the controller performance is not satisfactory, it has previously been suggested that the rule base be altered by combined tuning of membership functions and controller scaling factors. The alternative approach proposed here entails alteration of the fuzzy rule base. The recursive rule base adjustment algorithm proposed in this paper has the benefit that it is computationally more efficient for the generation of a DT, and advantage for online realization. Simulation results are presented to support this thesis. (c) 2005 Elsevier B.V. All rights reserved.

Strategies for Energy-Efficient Resource Management of Hybrid Programming Models

Many scientific applications are programmed using hybrid programming models that use both message passing and shared memory, due to the increasing prevalence of large-scale systems with multicore, multisocket nodes. Previous work has shown that energy efficiency can be improved using software-controlled execution schemes that consider both the programming model and the power-aware execution capabilities of the system. However, such approaches have focused on identifying optimal resource utilization for one programming model, either shared memory or message passing, in isolation. The potential solution space, thus the challenge, increases substantially when optimizing hybrid models since the possible resource configurations increase exponentially. Nonetheless, with the accelerating adoption of hybrid programming models, we increasingly need improved energy efficiency in hybrid parallel applications on large-scale systems. In this work, we present new software-controlled execution schemes that consider the effects of dynamic concurrency throttling (DCT) and dynamic voltage and frequency scaling (DVFS) in the context of hybrid programming models. Specifically, we present predictive models and novel algorithms based on statistical analysis that anticipate application power and time requirements under different concurrency and frequency configurations. We apply our models and methods to the NPB MZ benchmarks and selected applications from the ASC Sequoia codes. Overall, we achieve substantial energy savings (8.74 percent on average and up to 13.8 percent) with some performance gain (up to 7.5 percent) or negligible performance loss.

On the potential of significance-driven execution for energy-aware HPC

Dynamic Voltage and Frequency Scaling (DVFS) exhibits fundamental limitations as a method to reduce energy consumption in computing systems. In the HPC domain, where performance is of highest priority and codes are heavily optimized to minimize idle time, DVFS has limited opportunity to achieve substantial energy savings. This paper explores if operating processors Near the transistor Threshold Volt- age (NTV) is a better alternative to DVFS for break- ing the power wall in HPC. NTV presents challenges, since it compromises both performance and reliability to reduce power consumption. We present a first of its kind study of a significance-driven execution paradigm that selectively uses NTV and algorithmic error tolerance to reduce energy consumption in performance- constrained HPC environments. Using an iterative algorithm as a use case, we present an adaptive execution scheme that switches between near-threshold execution on many cores and above-threshold execution on one core, as the computational significance of iterations in the algorithm evolves over time. Using this scheme on state-of-the-art hardware, we demonstrate energy savings ranging between 35% to 67%, while compromising neither correctness nor performance.

TProf: An energy profiler for task-parallel programs

We present TProf, an energy profiling tool for OpenMP-like task-parallel programs. To compute the energy consumed by each task in a parallel application, TProf dynamically traces the parallel execution and uses a novel technique to estimate the per-task energy consumption. To achieve this estimation, TProf apportions the total processor energy among cores and overcomes the limitation of current works which would otherwise make parallel accounting impossible to achieve. We demonstrate the value of TProf by characterizing a set of task parallel programs, where we find that data locality, memory access patterns and task working sets are responsible for significant variance in energy consumption between seemingly homogeneous tasks. In addition, we identify opportunities for fine-grain energy optimization by applying per-task Dynamic Voltage and Frequency Scaling (DVFS).

Power-Capped DVFS and Thread Allocation with ANN Models on Modern NUMA Systems

Abstract—Power capping is an essential function for efficient power budgeting and cost management on modern server systems. Contemporary server processors operate under power caps by using dynamic voltage and frequency scaling (DVFS). However, these processors are often deployed in non-uniform memory
access (NUMA) architectures, where thread allocation between cores may significantly affect performance and power consumption. This paper proposes a method which maximizes performance under power caps on NUMA systems by dynamically optimizing two knobs: DVFS and thread allocation. The method selects the optimal combination of the two knobs with models based on artificial neural network (ANN) that captures the nonlinear effect of thread allocation on performance. We implement
the proposed method as a runtime system and evaluate it with twelve multithreaded benchmarks on a real AMD Opteron based NUMA system. The evaluation results show that our method outperforms a naive technique optimizing only DVFS by up to
67.1%, under a power cap.

Power Modeling and Capping for Heterogeneous ARM/FPGA SoCs

Low-power processors and accelerators that were originally designed for the embedded systems market are emerging as building blocks for servers. Power capping has been actively explored as a technique to reduce the energy footprint of high-performance processors. The opportunities and limitations of power capping on the new low-power processor and accelerator ecosystem are less understood. This paper presents an efficient power capping and management infrastructure for heterogeneous SoCs based on hybrid ARM/FPGA designs. The infrastructure coordinates dynamic voltage and frequency scaling with task allocation on a customised Linux system for the Xilinx Zynq SoC. We present a compiler-assisted power model to guide voltage and frequency scaling, in conjunction with workload allocation between the ARM cores and the FPGA, under given power caps. The model achieves less than 5% estimation bias to mean power consumption. In an FFT case study, the proposed power capping schemes achieve on average 97.5% of the performance of the optimal execution and match the optimal execution in 87.5% of the cases, while always meeting power constraints.

A quality-scalable and energy-efficient approach for spectral analysis of heart rate variability

Today there is a growing interest in the integration of health monitoring applications in portable devices necessitating the development of methods that improve the energy efficiency of such systems. In this paper, we present a systematic approach that enables energy-quality trade-offs in spectral analysis systems for bio-signals, which are useful in monitoring various health conditions as those associated with the heart-rate. To enable such trade-offs, the processed signals are expressed initially in a basis in which significant components that carry most of the relevant information can be easily distinguished from the parts that influence the output to a lesser extent. Such a classification allows the pruning of operations associated with the less significant signal components leading to power savings with minor quality loss since only less useful parts are pruned under the given requirements. To exploit the attributes of the modified spectral analysis system, thresholding rules are determined and adopted at design- and run-time, allowing the static or dynamic pruning of less-useful operations based on the accuracy and energy requirements. The proposed algorithm is implemented on a typical sensor node simulator and results show up-to 82% energy savings when static pruning is combined with voltage and frequency scaling, compared to the conventional algorithm in which such trade-offs were not available. In addition, experiments with numerous cardiac samples of various patients show that such energy savings come with a 4.9% average accuracy loss, which does not affect the system detection capability of sinus-arrhythmia which was used as a test case. 

Performance and Fault Tolerance of Preconditioned Iterative Solvers on Low-Power ARM Architectures

As the complexity of computing systems grows, reliability and energy are two crucial challenges asking for holistic solutions. In this paper, we investigate the interplay among concurrency, power dissipation, energy consumption and voltage-frequency scaling for a key numerical kernel for the solution of sparse linear systems. Concretely, we leverage a task-parallel implementation of the Conjugate Gradient method, equipped with an state-of-the-art pre-conditioner embedded in the ILUPACK software, and target a low-power multi core processor from ARM.In addition, we perform a theoretical analysis on the impact of a technique like Near Threshold Voltage Computing (NTVC) from the points of view of increased hardware concurrency and error rate.

Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics

The end of Dennard scaling has promoted low power consumption into a firstorder concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, xreliability. These limitations would make them unsuitable for HPC systems and datacenters. In order to demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM’s big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the paper describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.

Energy Optimization of Memory Intensive Parallel Workloads

Energy consumption is an important concern in modern multicore processors. The energy consumed by a multicore processor during the execution of an application can be minimized by tuning the hardware state utilizing knobs such as frequency, voltage etc. The existing theoretical work on energy minimization using Global DVFS (Dynamic Voltage and Frequency Scaling), despite being thorough, ignores the time and the energy consumed by the CPU on memory accesses and the dynamic energy consumed by the idle cores. This article presents an analytical energy-performance model for parallel workloads that accounts for the time and the energy consumed by the CPU chip on memory accesses in addition to the time and energy consumed by the CPU on CPU instructions. In addition, the model we present also accounts for the dynamic energy consumed by the idle cores. The existing work on global DVFS for parallel workloads shows that using a single frequency for the entire duration of a parallel application is not energy optimal and that varying the frequency according to the changes in the parallelism of the workload can save energy. We present an analytical framework around our energy-performance model to predict the operating frequencies (that depend upon the amount of parallelism) for global DVFS that minimize the overall CPU energy consumption. We show how the optimal frequencies in our model differ from the optimal frequencies in a model that does not account for memory accesses. We further show how the memory intensity of an application affects the optimal frequencies.

Power Stored and Quality Factors in Frequency Selective Surfaces at THz Frequencies

A study of the external, loaded and unloaded quality factors for frequency selective surfaces (FSSs) is presented. The study is focused on THz frequencies between 5 and 30 THz, where ohmic losses arising from the conductors become important. The influence of material properties, such as metal thickness, conductivity dispersion and surface roughness, is investigated. An equivalent circuit that models the FSS in the presence of ohmic losses is introduced and validated by means of full-wave results. Using both full-wave methods as well as a circuit model, the reactive energy stored in the vicinity of the FSS at resonance upon plane-wave incidence is presented. By studying a doubly periodic array of aluminium strips, it is revealed that the reactive power stored at resonance increases rapidly with increasing periodicity. Moreover, it is demonstrated that arrays with larger periodicity-and therefore less metallisation per unit area-exhibit stronger thermal absorption. Despite this absorption, arrays with higher periodicities produce higher unloaded quality factors. Finally, experimental results of a fabricated prototype operating at 14 THz are presented.

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.

Single-ionization of helium at Ti:sapphire wavelengths: rates and scaling laws

We present a numerical and theoretical study of intense-field single-electron ionization of helium at 390 nm and 780 nm. Accurate ionization rates (over an intensity range of (0.175-34) X10^14 W/ cm^2 at 390 nm, and (0.275 - 14.4) X 10^14 W /cm^2 at 780 nm) are obtained from full-dimensionality integrations of the time-dependent helium-laser Schroedinger equation. We show that the power law of lowest order perturbation theory, modified with a ponderomotive-shifted ionization potential, is capable of modelling the ionization rates over an intensity range that extends up to two orders of magnitude higher than that applicable to perturbation theory alone. Writing the modified perturbation theory in terms of scaled wavelength and intensity variables, we obtain to first approximation a single ionization law for both the 390 nm and 780 nm cases. To model the data in the high intensity limit as well as in the low, a new function is introduced for the rate. This function has, in part, a resemblance to that derived from tunnelling theory but, importantly, retains the correct frequency-dependence and scaling behaviour derived from the perturbative-like models at lower intensities. Comparison with the predictions of classical ADK tunnelling theory confirms that ADK performs poorly in the frequency and intensity domain treated here.

No association between hOGG1, XRCC1, and XPD polymorphisms and risk of reflux esophagitis, Barrett's Esophagus, or esophageal adenocarcinoma: Results from the factors influencing the Barrett's adenocarcinoma relationship case-control study

Reflux of gastric contents can lead to development of reflux esophagitis and Barrett's esophagus. Barrett's esophagus is a risk factor for esophageal adenocarcinoma. Damage to DNA may lead to carcinogenesis but is repaired through activation of pathways involving polymorphic enzymes, including human 8-oxoguanine glycosylase 1 (hOGG1), X-ray repair cross-complementing 1 (XRCC1), and xeroderma pigmentosum group D (XPD). Of the single nucleotide polymorphisms identified in these genes, hOGG1 Ser 326Cys, XRCC1 Arg 399Gln, and XPD Lys 751Gln are particularly common in Caucasians and have been associated with lower DNA repair capacity. Small studies have reported associations with XPD Lys 751Gln and esophageal adenocarcinoma. XRCC1 Arg 399Gln has been linked to Barrett's esophagus and reflux esophagitis. In a population-based case-control study, we examined associations of the hOGG1 Ser 326Cys, XRCC1 Arg 399Gln, and XPD Lys 751Gln polymorphisms with risk of esophageal adenocarcinoma, Barrett's esophagus, and reflux esophagitis. Genomic DNA was extracted from blood samples collected from cases of esophageal adenocarcinoma (n = 210), Barrett's esophagus (n = 212), reflux esophagitis (n = 230), and normal population controls frequency matched for age and sex (n = 248). Polymorphisms were genotyped using Taq-Man allelic discrimination assays. Odds ratios and 95% confidence intervals were obtained from logistic regression models adjusted for potential confounding factors. There were no statistically significant associations between these polymorphisms and risk of esophageal adenocarcinoma, Barrett's esophagus, or reflux esophagitis.