Reconfigurable video Motion Estimation processor

In this paper, a new reconfigurable multi-standard Motion Estimation (ME) architecture is proposed and a standard-cell based design study is presented. The architecture exhibits simpler control, high throughput and relative low hardware cost and is highly competitive when compared with existing designs for specific video standards. ©2007 IEEE.

Design and measurement of reconfigurable millileter wave reflectarray cells with nematic liquid crystal

Numerical simulations are used to study the electromagnetic scattering from phase agile microstrip reflectarray cells which exploit the voltage controlled dielectric anisotropy property of nematic state liquid crystals (LC). In the computer model two arrays of equal size elements constructed on a 15?m thick tuneable LC layer were designed to operate at centre frequencies of 102 GHz and 130 GHz. Micromachining processes based on the metallization of quartz/silicon wafers and an industry compatible LCD packaging technique were employed to fabricate the grounded periodic structures. The loss and phase of the reflected signals were measured using a quasi-optical test bench with the reflectarray cells inserted at the beam waist of the imaged Gaussian beam, thus eliminating some of the major problems associated with traditional free-space characterisation at these frequencies. By applying a low frequency AC bias voltage of 10 V, a 165o phase shift with a loss 4.5 dB-6.4 dB at 102 GHz and 130o phase shift with a loss variation between 4.3 dB – 7 dB at 130 GHz was obtained. The experimental results are shown to be in close agreement with the computer model.

Multiply reconfigurable ‘plug and play’ molecular logic via self-assembly

A substantial set of ion-driven molecular logic gates are implemented in turn by arranging the association between easily available lumophores and receptors in detergent micelles.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.