Risk-informed decision-making in the presence of epistemic uncertainty

An important issue in risk analysis is the distinction between epistemic and aleatory uncertainties. In this paper, the use of distinct representation formats for aleatory and epistemic uncertainties is advocated, the latter being modelled by sets of possible values. Modern uncertainty theories based on convex sets of probabilities are known to be instrumental for hybrid representations where aleatory and epistemic components of uncertainty remain distinct. Simple uncertainty representation techniques based on fuzzy intervals and p-boxes are used in practice. This paper outlines a risk analysis methodology from elicitation of knowledge about parameters to decision. It proposes an elicitation methodology where the chosen representation format depends on the nature and the amount of available information. Uncertainty propagation methods then blend Monte Carlo simulation and interval analysis techniques. Nevertheless, results provided by these techniques, often in terms of probability intervals, may be too complex to interpret for a decision-maker and we, therefore, propose to compute a unique indicator of the likelihood of risk, called confidence index. It explicitly accounts for the decisionmaker’s attitude in the face of ambiguity. This step takes place at the end of the risk analysis process, when no further collection of evidence is possible that might reduce the ambiguity due to epistemic uncertainty. This last feature stands in contrast with the Bayesian methodology, where epistemic uncertainties on input parameters are modelled by single subjective probabilities at the beginning of the risk analysis process.

SYSTOLIC IIR FILTERS WITH BIT LEVEL PIPELINING.

A novel bit-level systolic array architecture for implementing first-order IIR filter sections is presented. A latency of only two clock cycles is achieved by using a radix-4 redundant number representation, performing the recursive computation most-significant-digit first, and feeding back each digit of the result as soon as it is available.

Bit-level systolic arrays for IIR filtering.

A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.

A longitudinal analysis of estimation, counting skills, and mathematical ability across the first school year

In response to claims that the quality (and in particular linearity) of children's mental representation of number acts as a constraint on number development, we carried out a longitudinal assessment of the relationships between number line estimation, counting, and mathematical abilities. Ninety-nine 5-year-olds were tested on 4 occasions at 3 monthly intervals. Correlations between the 3 types of ability were evident, but while the quality of children's estimations changed over time and performance on the mathematical tasks improved over the same period, changes in one were not associated with changes in the other. In contrast to the earlier claims that the linearity of number representation is potentially a unique contributor to children's mathematical development, the data suggest that this variable is not significantly privileged in its impact over and above simple procedural number skills. We propose that both early arithmetic success and estimating skill are bound closely to developments in counting ability.

A high performance IIR digital filter chip

The design of a high-performance IIR (infinite impulse response) digital filter is described. The chip architecture operates on 11-b parallel, two's complement input data with a 12-b parallel two's complement coefficient to produce a 14-b two's complement output. The chip is implemented in 1.5-µm, double-layer-metal CMOS technology, consumes 0.5 W, and can operate up to 15 Msample/s. The main component of the system is a fine-grained systolic array that internally is based on a signed binary number representation (SBNR). Issues addressed include testing, clock distribution, and circuitry for conversion between two's complement and SBNR.

Explaining the multiparty systems of Western Europe prior to the adoption of proportional representation

The literature has difficulty explaining why the number of parties in majoritarian electoral systems often exceeds the two-party predictions associated with Duverger’s Law. To understand why this is the case, I examine several party systems in Western Europe before the adoption of proportional representation. Drawing from the social cleavage approach, I argue that the emergence of multiparty systems was because of the development of the class cleavage, which provided a base of voters sizeable enough to support third parties. However, in countries where the class cleavage became the largest cleavage, the class divide displaced other cleavages and the number of parties began to converge on two. The results show that the effect of the class cleavage was nonlinear, producing the greatest party system fragmentation in countries where class cleavages were present – but not dominant – and smaller in countries where class cleavages were either dominant or non-existent.