Reconfigurable cryptographic RISC microprocessor

This paper describes a novel RISC microprocessor that can be utilised to rapidly develop a reprogrammable and high performance embedded security-processing system in SoC designs. Generic and innovative algorithm-specific instructions have been developed for a wide range of private-key and hash algorithms. To the authors' knowledge, this is the first generic cryptographic microprocessor to be reported in the literature.

Short interfering RNA-mediated gene silencing in Globodera pallida and Meloidogyne incognita infective stage juveniles

The analysis of gene function through RNA interference (RNAi)-based reverse genetics in plant parasitic nematodes (PPNs) remains inexplicably reliant on the use of long double-stranded RNA (dsRNA) silencing triggers; a practice inherently disadvantageous due to the introduction of superfluous dsRNA sequence. increasing chances of aberrant or off-target gene silencing through interactions between nascent short interfering RNAs (siRNAs) and non-cognate mRNA targets. Recently, we have shown that non-nematode, long dsRNAs have a propensity to elicit profound impacts on the phenotype and migrational abilities of both root knot and cyst nematodes. This study presents, to our knowledge for the first time, gene-specific knockdown of FMRFamide-like peptide (flp) transcripts, using discrete 21 bp siRNAs in potato cyst nematode Globodera pallida, and root knot nematode Meloidogyne incognita infective (J2) stage juveniles. Both knockdown at the transcript level through quantitative (q)PCR analysis and functional data derived from migration assay, indicate that siRNAs targeting certain areas of the FMRFamide-like peptide (FLP) transcripts are potent and specific in the silencing of gene function. In addition, we present a method of manipulating siRNA activity through the management of strand thermodynamics. Initial evaluation of strand thermodynamics as a determinant of RNA-induced Silencing Complex (RISC) strand selection (inferred from knockdown efficacy) in the siRNAs presented here suggested that the purported influence of 5' stand stability on guide incorporation may be somewhat promiscuous. However, we have found that on strategically incorporating base mismatches in the sense strand of a G. pallida-specific siRNA we could specifically increase or decrease the knockdown of its target (specific to the antisense strand), presumably through creating more favourable thermodynamic profiles for incorporation of either the sense (non-target-specific) or antisense (target-specific) strand into a cleavage-competent RISC. Whilst the efficacy of similar approaches to siRNA modification has been demonstrated in the context of Drosophila whole-cell lysate preparations and in mammalian cell cultures, it remained to be seen how these sense strand mismatches may impact on gene silencing in vivo, in relation to different targets and in different sequence contexts. This work presents the first application of such an approach in a whole organism; initial results show promise. (C) 2009 Australian Society for Parasitology Inc. Published by Elsevier Ltd. All rights reserved.

IPPro: FPGA based Image Processing Processor

The paper presents IPPro which is a high performance, scalable soft-core processor targeted for image processing applications. It has been based on the Xilinx DSP48E1 architecture using the ZYNQ Field Programmable Gate Array and is a scalar 16-bit RISC processor that operates at 526MHz, giving 526MIPS of performance. Each IPPro core uses 1 DSP48, 1 Block RAM and 330 Kintex-7 slice-registers, thus making the processor as compact as possible whilst maintaining flexibility and programmability. A key aspect of the approach is in reducing the application design time and implementation effort by using multiple IPPro processors in a SIMD mode. For different applications, this allows us to exploit different levels of parallelism and mapping for the specified processing architecture with the supported instruction set. In this context, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the colour and morphology operations accelerated using multiple IPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 to 33 times for colour filtering and morphology operations respectively, with a reduced design effort and time.

Design patterns percolating to parallel programming framework implementation

Structured parallel programming is recognised as a viable and effective means of tackling parallel programming problems. Recently, a set of simple and powerful parallel building blocks RISC pb²l) has been proposed to support modelling and implementation of parallel frameworks. In this work we demonstrate how that same parallel building block set may be used to model both general purpose parallel programming abstractions, not usually listed in classical skeleton sets, and more specialized domain specific parallel patterns. We show how an implementation of RISC pb² l can be realised via the FastFlow framework and present experimental evidence of the feasibility and efficiency of the approach.

A low overhead error confinement method based on application statistical characteristics

Reliability has emerged as a critical design constraint especially in memories. Designers are going to great lengths to guarantee fault free operation of the underlying silicon by adopting redundancy-based techniques, which essentially try to detect and correct every single error. However, such techniques come at a cost of large area, power and performance overheads which making many researchers to doubt their efficiency especially for error resilient systems where 100% accuracy is not always required. In this paper, we present an alternative method focusing on the confinement of the resulting output error induced by any reliability issues. By focusing on memory faults, rather than correcting every single error the proposed method exploits the statistical characteristics of any target application and replaces any erroneous data with the best available estimate of that data. To realize the proposed method a RISC processor is augmented with custom instructions and special-purpose functional units. We apply the method on the proposed enhanced processor by studying the statistical characteristics of the various algorithms involved in a popular multimedia application. Our experimental results show that in contrast to state-of-the-art fault tolerance approaches, we are able to reduce runtime and area overhead by 71.3% and 83.3% respectively.