Multiple Luminaire Identification in Airborne Images of Airport’s Approach Lighting Using Mathematical Morphology With Variable Length Structuring Element

The increasing demand for fast air transportation around the clock
has increased the number of night flights in civil aviation over
the past few decades. In night aviation, to land an aircraft, a
pilot needs to be able to identify an airport. The approach
lighting system (ALS) at an airport is used to provide
identification and guidance to pilots from a distance. ALS
consists of more than $100$ luminaires which are installed in a
defined pattern following strict guidelines by the International
Civil Aviation Organization (ICAO). ICAO also has strict
regulations for maintaining the performance level of the
luminaires. However, once installed, to date there is no automated
technique by which to monitor the performance of the lighting. We
suggest using images of the lighting pattern captured using a camera
placed inside an aircraft. Based on the information contained
within these images, the performance of the luminaires has to be
evaluated which requires identification of over $100$ luminaires
within the pattern of ALS image. This research proposes analysis
of the pattern using morphology filters which use a variable
length structuring element (VLSE). The dimension of the VLSE changes
continuously within an image and varies for different images.
A novel
technique for automatic determination of the VLSE is proposed and
it allows successful identification of the luminaires from the
image data as verified through the use of simulated and real data.

IPPro: FPGA based Image Processing Processor

The paper presents IPPro which is a high performance, scalable soft-core processor targeted for image processing applications. It has been based on the Xilinx DSP48E1 architecture using the ZYNQ Field Programmable Gate Array and is a scalar 16-bit RISC processor that operates at 526MHz, giving 526MIPS of performance. Each IPPro core uses 1 DSP48, 1 Block RAM and 330 Kintex-7 slice-registers, thus making the processor as compact as possible whilst maintaining flexibility and programmability. A key aspect of the approach is in reducing the application design time and implementation effort by using multiple IPPro processors in a SIMD mode. For different applications, this allows us to exploit different levels of parallelism and mapping for the specified processing architecture with the supported instruction set. In this context, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the colour and morphology operations accelerated using multiple IPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 to 33 times for colour filtering and morphology operations respectively, with a reduced design effort and time.

FPGA based Streaming Image Processing Processor (SIPPro) architecture to accelerate data intensive applications

Current data-intensive image processing applications push traditional embedded architectures to their limits. FPGA based hardware acceleration is a potential solution but the programmability gap and time consuming HDL design flow is significant. The proposed research approach to develop “FPGA based programmable hardware acceleration platform” that uses, large number of Streaming Image processing Processors (SIPPro) potentially addresses these issues. SIPPro is pipelined in-order soft-core processor architecture with specific optimisations for image processing applications. Each SIPPro core uses 1 DSP48, 2 Block RAMs and 370 slice-registers, making the processor as compact as possible whilst maintaining flexibility and programmability. It is area efficient, scalable and high performance softcore architecture capable of delivering 530 MIPS per core using Xilinx Zynq SoC (ZC7Z020-3). To evaluate the feasibility of the proposed architecture, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the color and morphology operations accelerated using multiple SIPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 and 33 times for color filtering and morphology operations respectively, with a significant reduced design effort and time.