Automatic FPGA Synthesis of Memory Intensive C-based Kernels

Realising high performance image and signal processing
applications on modern FPGA presents a challenging implementation problem due to the large data frames streaming through these systems. Specifically, to meet the high bandwidth and data storage demands of these applications, complex hierarchical memory architectures must be manually specified
at the Register Transfer Level (RTL). Automated approaches which convert high-level operation descriptions, for instance in the form of C programs, to an FPGA architecture, are unable to automatically realise such architectures. This paper
presents a solution to this problem. It presents a compiler to automatically derive such memory architectures from a C program. By transforming the input C program to a unique dataflow modelling dialect, known as Valved Dataflow (VDF), a mapping and synthesis approach developed for this dialect can
be exploited to automatically create high performance image and video processing architectures. Memory intensive C kernels for Motion Estimation (CIF Frames at 30 fps), Matrix Multiplication (128x128 @ 500 iter/sec) and Sobel Edge Detection (720p @ 30 fps), which are unrealisable by current state-of-the-art C-based synthesis tools, are automatically derived from a C description of the algorithm.

Who is responsible?:The role of family physicians in the provision of supportive cancer care

Purpose: Patients living with cancer identify family physicians (FPs; ie, primary care physicians) as a preferred resource for supportive cancer care (SCC), either through direct provision or referral. However, little research exists on the specific role FPs play in addressing these needs. Methods: A mailed survey was sent to all FPs in a health care region in Ontario, Canada, to determine their current and preferred roles in the specific provision of SCC to patients with cancer who have been newly diagnosed or are at the end of life. Results: Completed surveys were received from 84 (64%) of 183 eligible FPs. Most practitioners reported providing for their patients' various SCC needs. However, clear gaps were demonstrated in psychosocial and nutritional counseling and in providing information about SCC services. FPs were satisfied with their current role reported in SCC coordination, although the type of role varied; FPs who were asked about their end-of-life patients tended to see themselves as part of coordinating teams, whereas FPs asked about their recently diagnosed patients were more likely to defer this responsibly to a third party. Conclusion: This study identified gaps in the provision of psychosocial and informational care to patients with cancer that may result in unmet needs. In general, FPs do not see themselves as primarily responsible for coordinating patients' SCC and do not wish to assume this role. Accordingly, models that involve FPs as team members in SCC coordination are more feasible for reducing patient need. Copyright © 2010 by American Society of Clinical Oncology.

FPGA Soft-core Processors, Compiler and Hardware Optimizations validated using HOG

There is demand for an easily programmable, high performance image processing platform based on FPGAs. In previous work, a novel, high performance processor - IPPro was developed and a Histogram of Orientated Gradients (HOG) algorithm study undertaken on a Xilinx Zynq platform. Here, we identify and explore a number of mapping strategies to improve processing efficiency for soft-cores and a number of options for creation of a division coprocessor. This is demonstrated for the revised high definition HOG implementation on a Zynq platform, resulting in a performance of 328 fps which represents a 146% speed improvement over the original realization and a tenfold reduction in energy.

FPGA-based soft-core processors for image processing applications

With security and surveillance, there is an increasing need to process image data efficiently and effectively either at source or in a large data network. Whilst a Field-Programmable Gate Array (FPGA) has been seen as a key technology for enabling this, the design process has been viewed as problematic in terms of the time and effort needed for implementation and verification. The work here proposes a different approach of using optimized FPGA-based soft-core processors which allows the user to exploit the task and data level parallelism to achieve the quality of dedicated FPGA implementations whilst reducing design time. The paper also reports some preliminary
progress on the design flow to program the structure. An implementation for a Histogram of Gradients algorithm is also reported which shows that a performance of 328 fps can be achieved with this design approach, whilst avoiding the long design time, verification and debugging steps associated with conventional FPGA implementations.