Hybrid FIB milling strategy for the fabrication of plasmonic nanostructures on semiconductor substrates

The optical properties of plasmonic semiconductor devices fabricated by focused ion beam (FIB) milling deteriorate because of the amorphisation of the semiconductor substrate. This study explores the effects of combining traditional 30 kV FIB milling with 5 kV FIB patterning to minimise the semiconductor damage and at the same time maintain high spatial resolution. The use of reduced acceleration voltages is shown to reduce the damage from higher energy ions on the example of fabrication of plasmonic crystals on semiconductor substrates leading to 7-fold increase in transmission. This effect is important for focused-ion beam fabrication of plasmonic structures integrated with photodetectors, light-emitting diodes and semiconductor lasers.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.