16 resultados para Electronic optimization

em QUB Research Portal - Research Directory and Institutional Repository for Queen's University Belfast


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This study was carried out to investigate whether the electronic portal imaging (EPI) acquisition process could be optimized, and as a result tolerance and action levels be set for the PIPSPro QC-3V phantom image quality assessment. The aim of the optimization process was to reduce the dose delivered to the patient while maintaining a clinically acceptable image quality. This is of interest when images are acquired in addition to the planned patient treatment, rather than images being acquired using the treatment field during a patient's treatment. A series of phantoms were used to assess image quality for different acquisition settings relative to the baseline values obtained following acceptance testing. Eight Varian aS500 EPID systems on four matched Varian 600C/D linacs and four matched Varian 2100C/D linacs were compared for consistency of performance and images were acquired at the four main orthogonal gantry angles. Images were acquired using a 6 MV beam operating at 100 MU min(-1) and the low-dose acquisition mode. Doses used in the comparison were measured using a Farmer ionization chamber placed at d(max) in solid water. The results demonstrated that the number of reset frames did not have any influence on the image contrast, but the number of frame averages did. The expected increase in noise with corresponding decrease in contrast was also observed when reducing the number of frame averages. The optimal settings for the low-dose acquisition mode with respect to image quality and dose were found to be one reset frame and three frame averages. All patients at the Northern Ireland Cancer Centre are now imaged using one reset frame and three frame averages in the 6 MV 100 MU min(-1) low-dose acquisition mode. Routine EPID QC contrast tolerance (+/-10) and action (+/-20) levels using the PIPSPro phantom based around expected values of 190 (Varian 600C/D) and 225 (Varian 2100C/D) have been introduced. The dose at dmax from electronic portal imaging has been reduced by approximately 28%, and while the image quality has been reduced, the images produced are still clinically acceptable.

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An overview of a many-body approach to calculation of electronic transport in molecular systems is given. The physics required to describe electronic transport through a molecule at the many-body level, without relying on commonly made assumptions such as the Landauer formalism or linear response theory, is discussed. Physically, our method relies on the incorporation of scattering boundary conditions into a many-body wavefunction and application of the maximum entropy principle to the transport region. Mathematically, this simple physical model translates into a constrained nonlinear optimization problem. A strategy for solving the constrained optimization problem is given. (C) 2004 Wiley Periodicals, Inc.

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An efficient method for calculating the electronic structure of systems that need a very fine sampling of the Brillouin zone is presented. The method is based on the variational optimization of a single (i.e., common to all points in the Brillouin zone) basis set for the expansion of the electronic orbitals. Considerations from k.p-approximation theory help to understand the efficiency of the method. The accuracy and the convergence properties of the method as a function of the optimal basis set size are analyzed for a test calculation on a 16-atom Na supercell.

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In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-kappa gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I-on/I-off). Based on the investigation of on-current (I-on), off-current (I-off), I-on/I-off, intrinsic delay (tau), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/sigma) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I-on, I-off and tau is also investigated for optimized underlap devices.

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In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

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A physically open, but electrically shielded, microwave open oven can be produced by virtue of the evanescent fields in a waveguide below cutoff. The below cutoff heating chamber is fed by a transverse magnetic resonance established in a dielectric-filled section of the waveguide exploiting continuity of normal electric flux. In order to optimize the fields and the performance of the oven, a thin layer of a dielectric material with higher permittivity is inserted at the interface. Analysis and synthesis of an optimized open oven predicts field enhancement in the heating chamber up to 9.4 dB. Results from experimental testing on two fabricated prototypes are in agreement with the simulated predictions, and demonstrate an up to tenfold improvement in the heating performance. The open-ended oven allows for simultaneous precision alignment, testing, and efficient curing of microelectronic devices, significantly increasing productivity gains.

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This paper presents an optimization-based approach to the design of asymmetrical filter structures having the maximum number of return- or insertion-loss ripples in the passband such as those based upon Chebyshev function prototypes. The proposed approach. has the following advantages over the general purpose optimization techniques adopted previously such as: less frequency sampling is required, optimization is carried out with respect to the Chebyshev (or minimax) criterion, the problem of local minima does not arise, and optimization is usually only required for the passband. When implemented around an accurate circuit simulation, the method can be used to include all the effects of discontinuities, junctions, fringing, etc. to reduce the amount of tuning required in the final filter. The design of asymmetrical ridged-waveguide bandpass filters is considered as an example. Measurements on a fabricated filter confirm the accuracy of the design procedure.

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Here we consider the numerical optimization of active surface plasmon polariton (SPP) trench waveguides suited for integration with luminescent polymers for use as highly localized SPP source devices in short-scale communication integrated circuits. The numerical analysis of the SPP modes within trench waveguide systems provides detailed information on the mode field components, effective indices, propagation lengths and mode areas. Such trench waveguide systems offer extremely high confinement with propagation on length scales appropriate to local interconnects, along with high efficiency coupling of dipolar emitters to waveguided plasmonic modes which can be close to 80%. The large Purcell factor exhibited in these structures will further lead to faster modulation capabilities along with an increased quantum yield beneficial for the proposed plasmon-emitting diode, a plasmonic analog of the light-emitting diode. The confinement of studied guided modes is on the order of 50 nm and the delay over the shorter 5 μm length scales will be on the order of 0.1 ps for the slowest propagating modes of the system, and significantly less for the faster modes.

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Insulated-gate bipolar transistor (IGBT) power modules find widespread use in numerous power conversion applications where their reliability is of significant concern. Standard IGBT modules are fabricated for general-purpose applications while little has been designed for bespoke applications. However, conventional design of IGBTs can be improved by the multiobjective optimization technique. This paper proposes a novel design method to consider die-attachment solder failures induced by short power cycling and baseplate solder fatigue induced by the thermal cycling which are among major failure mechanisms of IGBTs. Thermal resistance is calculated analytically and the plastic work design is obtained with a high-fidelity finite-element model, which has been validated experimentally. The objective of minimizing the plastic work and constrain functions is formulated by the surrogate model. The nondominated sorting genetic algorithm-II is used to search for the Pareto-optimal solutions and the best design. The result of this combination generates an effective approach to optimize the physical structure of power electronic modules, taking account of historical environmental and operational conditions in the field.

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Heat sinks are widely used for cooling electronic devices and systems. Their thermal performance is usually determined by the material, shape, and size of the heat sink. With the assistance of computational fluid dynamics (CFD) and surrogate-based optimization, heat sinks can be designed and optimized to achieve a high level of performance. In this paper, the design and optimization of a plate-fin-type heat sink cooled by impingement jet is presented. The flow and thermal fields are simulated using the CFD simulation; the thermal resistance of the heat sink is then estimated. A Kriging surrogate model is developed to approximate the objective function (thermal resistance) as a function of design variables. Surrogate-based optimization is implemented by adaptively adding infill points based on an integrated strategy of the minimum value, the maximum mean square error approach, and the expected improvement approaches. The results show the influence of design variables on the thermal resistance and give the optimal heat sink with lowest thermal resistance for given jet impingement conditions. 

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The applicability of ultra-short-term wind power prediction (USTWPP) models is reviewed. The USTWPP method proposed extracts featrues from historical data of wind power time series (WPTS), and classifies every short WPTS into one of several different subsets well defined by stationary patterns. All the WPTS that cannot match any one of the stationary patterns are sorted into the subset of nonstationary pattern. Every above WPTS subset needs a USTWPP model specially optimized for it offline. For on-line application, the pattern of the last short WPTS is recognized, then the corresponding prediction model is called for USTWPP. The validity of the proposed method is verified by simulations.