Low-cost digital signature architecture suitable for radio frequency identification tags

Continuing achievements in hardware technology are bringing ubiquitous computing closer to reality. The notion of a connected, interactive and autonomous environment is common to all sensor networks, biosystems and radio frequency identification (RFID) devices, and the emergence of significant deployments and sophisticated applications can be expected. However, as more information is collected and transmitted, security issues will become vital for such a fully connected environment. In this study the authors consider adding security features to low-cost devices such as RFID tags. In particular, the authors consider the implementation of a digital signature architecture that can be used for device authentication, to prevent tag cloning, and for data authentication to prevent transmission forgery. The scheme is built around the signature variant of the cryptoGPS identification scheme and the SHA-1 hash function. When implemented on 130 nm CMOS the full design uses 7494 gates and consumes 4.72 mu W of power, making it smaller and more power efficient than previous low-cost digital signature designs. The study also presents a low-cost SHA-1 hardware architecture which is the smallest standardised hash function design to date.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

Prostate cancer radiotherapy: potential applications of metal nanoparticles for imaging and therapy

Prostate cancer (CaP) is the most commonly diagnosed cancer in males. There have been dramatic technical advances in radiotherapy delivery, enabling higher doses of radiotherapy to primary cancer, involved lymph nodes and oligometastases with acceptable normal tissue toxicity. Despite this, many patients relapse following primary radical therapy, and novel treatment approaches are required. Metal nanoparticles are agents that promise to improve diagnostic imaging and image-guided radiotherapy and to selectively enhance radiotherapy effectiveness in CaP. We summarize current radiotherapy treatment approaches for CaP and consider pre-clinical and clinical evidence for metal nanoparticles in this condition.

Prostate cancer (CaP) is the most commonly diagnosed cancer in males and is responsible for more than 10,000 deaths each year in the UK.1 Technical advances in radiotherapy delivery, including image-guided intensity-modulated radiotherapy (IG-IMRT), have enabled the delivery of higher radiation dose to the prostate, which has led to improved biochemical control. Further improvements in cancer imaging during radiotherapy are being developed with the advent of MRI simulators and MRI linear accelerators.2–4

Nanotechnology promises to deliver significant advancements across numerous disciplines.5 The widest scope of applications are from the biomedical field including exogenous gene/drug delivery systems, advanced biosensors, targeted contrast agents for diagnostic applications and as direct therapeutic agents used in combination with existing treatment modalities.6–11 This diversity of application is especially evident within cancer research, with a myriad of experimental anticancer strategies currently under investigation.

This review will focus specifically on the potential of metal-based nanoparticles to augment the efficacy of radiotherapy in CaP, a disease where radiotherapy constitutes a major curative treatment modality.12 Furthermore, we will also address the clinical state of the art for CaP radiotherapy and consider how these treatments could be best combined with nanotherapeutics to improve cancer outcomes.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Efficient advanced encryption standard implementation using lookup and normal basis

A new type of advanced encryption standard (AES) implementation using a normal basis is presented. The method is based on a lookup technique that makes use of inversion and shift registers, which leads to a smaller size of lookup for the S-box than its corresponding implementations. The reduction in the lookup size is based on grouping sets of inverses into conjugate sets which in turn leads to a reduction in the number of lookup values. The above technique is implemented in a regular AES architecture using register files, which requires less interconnect and area and is suitable for security applications. The results of the implementation are competitive in throughput and area compared with the corresponding solutions in a polynomial basis.

Dynamic global security-aware synthesis using System-C

A dynamic global security-aware synthesis flow using the SystemC language is presented. SystemC security models are first specified at the system or behavioural level using a library of SystemC behavioural descriptions which provide for the reuse and extension of security modules. At the core of the system is incorporated a global security-aware scheduling algorithm which allows for scheduling to a mixture of components of varying security level. The output from the scheduler is translated into annotated nets which are subsequently passed to allocation, optimisation and mapping tools for mapping into circuits. The synthesised circuits incorporate asynchronous secure power-balanced and fault-protected components. Results show that the approach offers robust implementations and efficient security/area trade-offs leading to significant improvements in turnover.

High power laser production of short-lived isotopes for positron emission tomography

Positron emission tomography (PET) is a powerful diagnostic/imaging technique requiring the production of the short-lived positron emitting isotopes C-11, N-13, O-15 and F-18 by proton irradiation of natural/enriched targets using cyclotrons. The development of PET has been hampered due to the size and shielding requirements of nuclear installations. Recent results show that when an intense laser beam interacts with solid targets, megaelectronvolt (MeV) protons capable of producing PET isotopes are generated. This report describes how to generate intense PET sources of C-11 and F-18 using a petawatt laser beam. The work describing the laser production of F-18 through a (p,n) O-18 reaction, and the subsequent synthesis of 2-[F-18] is reported for the first time. The potential for developing compact laser technology for this purpose is discussed.

VLSI module for high-performance multiply, square root and divide

A high-performance VLSI architecture to perform multiply-accumulate, division and square root operations is proposed. The circuit is highly regular, requires only minimal control and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform any one of these operations. The gate count per row has been estimated at (27n+70) gate equivalents where n is the divisor wordlength. The throughput rate, which equals the clock speed, is the same for each operation and is independent of the wordlength. This is achieved through the combination of pipelining and redundant arithmetic. With a 1.0 µm CMOS technology and extensive pipelining, throughput rates in excess of 70 million operations per second are expected.

Gold nanoparticle surface functionalization: a necessary requirement in the development of novel nanotherapeutics

With several gold nanoparticle-based therapies currently undergoing clinical trials, these treatments may soon be in the clinic as novel anticancer agents. Gold nanoparticles are the subject of a wide ranging international research effort with preclinical studies underway for multiple applications including photoablation, diagnostic imaging, radiosensitization and multifunctional drug-delivery vehicles. These applications require an increasingly complex level of surface modification in order to achieve efficacy and limit off-target toxicity. This review will discuss the main obstacles in relation to surface functionalization and the chemical approaches commonly utilized. Finally, we review a range of recent preclinical studies that aim to advance gold nanoparticle treatments toward the clinic.

Experimental investigation of flow and segregation behaviour of bulk solids in silos under high gravity conditions

Many researchers have investigated the flow and segregation behaviour in model scale experimental silos at normal gravity conditions. However it is known that the stresses experienced by the bulk solid in industrial silos are high when compared to model silos. Therefore it is important to understand the effect of stress level on flow and segregation behaviour and establish the scaling laws governing this behaviour. The objective of this paper is to understand the effect of gravity on the flow and segregation behaviour of bulk solids in a silo centrifuge model. The materials used were two mixtures composed of Polyamide and glass beads. The discharge of two bi-disperse bulk solids in a silo centrifuge model were recorded under accelerations ranging from 1g to 15g. The velocity distribution during discharge was evaluated using Particle Image Velocimetry (PIV) techniques and the concentration distribution of large and small particles were obtained by imaging processing techniques. The flow and segregation behaviour at high gravities were then quantified and compared with the empirical equations available in the literature.