WLAN Security Processor

A novel wireless local area network (WLAN) security processor is described in this paper. It is designed to offload security encapsulation processing from the host microprocessor in an IEEE 802.11i compliant medium access control layer to a programmable hardware accelerator. The unique design, which comprises dedicated cryptographic instructions and hardware coprocessors, is capable of performing wired equivalent privacy, temporal key integrity protocol, counter mode with cipher block chaining message authentication code protocol, and wireless robust authentication protocol. Existing solutions to wireless security have been implemented on hardware devices and target specific WLAN protocols whereas the programmable security processor proposed in this paper provides support for all WLAN protocols and thus, can offer backwards compatibility as well as future upgrade ability as standards evolve. It provides this additional functionality while still achieving equivalent throughput rates to existing architectures. © 2006 IEEE.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

Eliciting and estimating valid subjective probabilities: An experimental investigation of the Exchangeability Method.

Using a laboratory experiment, we investigate whether incentive compatibility affects subjective probabilities elicited via the exchangeability method (EM), an elicitation technique consisting of several chained questions. We hypothesize that subjects who are aware of the chaining strategically behave and provide invalid subjective probabilities, while subjects who are not aware of the chaining state their real beliefs and provide valid subjective probabilities. The validity of subjective probabilities is investigated using de Finetti's notion of coherence, under which probability estimates are valid if and only if they obey all axioms of probability theory.
Four experimental treatments are designed and implemented. Subjects are divided into two initial treatment groups: in the first, they are provided with real monetary incentives, and in the second, they are not. Each group is further sub-divided into two treatment groups, in the first, the chained structure of the experimental design is made clear to the subjects, while, in the second, the chained structure is hidden by randomizing the elicitation questions.
Our results suggest that subjects provided with monetary incentives and randomized questions provide valid subjective probabilities because they are not aware of the chaining which undermines the incentive compatibility of the exchangeability method.