103 resultados para ASYMMETRIC DIVISION

em QUB Research Portal - Research Directory and Institutional Repository for Queen's University Belfast


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Zygotes of the fucoid brown algae provide excellent models for addressing fundamental questions about zygotic symmetry breaking. Although the acquisition of polarity is tightly coordinated with the timing and orientation of the first asymmetric division-with zygotes having to pass through a G1/S-phase checkpoint before the polarization axis can be fixed -the mechanisms behind the interdependence of polarization and cell cycle progression remain unclear. In this study, we combine in vivo Ca(2+) imaging, single cell monitoring of S-phase progression and multivariate analysis of high-throughput intracellular Ca(2+) buffer loading to demonstrate that Ca(2+) signals coordinate polarization and cell cycle progression in the Fucus serratus zygote. Consistent with earlier studies on this organism, and in contrast to animal models, we observe no fast Ca(2+) wave following fertilization. Rather, we show distinct slow localized Ca(2+) elevations associated with both fertilization and S-phase progression, and we show that both S-phase and zygotic polarization are dependent on pre-S-phase Ca(2+) increases. Surprisingly, this Ca(2+) requirement cannot be explained by co-dependence on a single G1/ S-phase checkpoint, as S phase and zygotic polarization are differentially sensitive to pre-S-phase Ca(2+) elevations and can be uncoupled. Furthermore, subsequent cell cycle progression through M phase is independent of localized actin polymerization and zygotic polarization. This absence of a morphogenesis checkpoint, together with the observed Ca(2+)dependences of S phase and polarization, show that the regulation of zygotic division in the brown algae differs from that in other eukaryotic model systems, such as yeast and Drosophila.

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In this paper, we discuss and evaluate two proposed metro wavelength division multiplexing (WDM) ring network architectures for variable-length packet traffic in storage area networks (SANs) settings. The paper begins with a brief review of the relevant architectures and protocols in the literature. Subsequently, the network architectures along with their medium access control (MAC) protocols are described. Performance of the two network architectures is studied by means of computer simulation in terms of their queuing delay, node throughput and proportion of packets dropped. The network performance is evaluated under symmetric and asymmetric traffic scenarios with Poisson and self-similar traffic. (C) 2011 Elsevier Inc. All rights reserved.

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We investigate the group valued functor G(D) = D*/F*D' where D is a division algebra with center F and D' the commutator subgroup of D*. We show that G has the most important functorial properties of the reduced Whitehead group SK1. We then establish a fundamental connection between this group, its residue version, and relative value group when D is a Henselian division algebra. The structure of G(D) turns out to carry significant information about the arithmetic of D. Along these lines, we employ G(D) to compute the group SK1(D). As an application, we obtain theorems of reduced K-theory which require heavy machinery, as simple examples of our method.

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We propose an optimal strategy for continuous-variable teleportation in a realistic situation. We show that the typical imperfect quantum operation can be described as a combination of an asymmetrically decohered quantum channel and perfect apparatuses for other operations. For the asymmetrically decohered quantum channel, we find some counterintuitive results: teleportation does not necessarily get better as the channel is initially squeezed more. We show that decoherence-assisted measurement and transformation may enhance fidelity for an asymmetrically mixed quantum channel.

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In this paper a novel scalable public-key processor architecture is presented that supports modular exponentiation and Elliptic Curve Cryptography over both prime GF(p) and binary GF(2) extension fields. This is achieved by a high performance instruction set that provides a comprehensive range of integer and polynomial basis field arithmetic. The instruction set and associated hardware are generic in nature and do not specifically support any cryptographic algorithms or protocols. Firmware within the device is used to efficiently implement complex and data intensive arithmetic. A firmware library has been developed in order to demonstrate support for numerous exponentiation and ECC approaches, such as different coordinate systems and integer recoding methods. The processor has been developed as a high-performance asymmetric cryptography platform in the form of a scalable Verilog RTL core. Various features of the processor may be scaled, such as the pipeline width and local memory subsystem, in order to suit area, speed and power requirements. The processor is evaluated and compares favourably with previous work in terms of performance while offering an unparalleled degree of flexibility. © 2006 IEEE.