209 resultados para Multiprocessor computer architectures


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Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues in terms of memory organisation and accesses when developing systems from these high level representations. Using a template matching design study, challenges such as modelling memory reuse and minimising buffer requirements are examined, yielding results with significantly less memory requirements and costly off-chip memory accesses.

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Ensuring that all graduates are able to exploit new technologies is a primary goal of all UK universities and a variety of assumptions have underpinned policies designed to promote this goal, This paper explores some of these assumptions through the findings of a. longitudinal study involving a cohort of over 800 university students. The study adopted a student perspective to examine the factors affecting their use of computers over a three year period. Unsurprisingly, the results indicated that situational factors (e.g. access, training and time) influence the extent to which students use computers, but a disparity was found in the importance attributed to these factors by the academic staff, who focused on the needs of their department, and by the students, who focused on their individual needs. Results suggest that increased attention to a student perspective may lead to improved strategic planning in students' use of computers.

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Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.

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In this paper, a novel video-based multimodal biometric verification scheme using the subspace-based low-level feature fusion of face and speech is developed for specific speaker recognition for perceptual human--computer interaction (HCI). In the proposed scheme, human face is tracked and face pose is estimated to weight the detected facelike regions in successive frames, where ill-posed faces and false-positive detections are assigned with lower credit to enhance the accuracy. In the audio modality, mel-frequency cepstral coefficients are extracted for voice-based biometric verification. In the fusion step, features from both modalities are projected into nonlinear Laplacian Eigenmap subspace for multimodal speaker recognition and combined at low level. The proposed approach is tested on the video database of ten human subjects, and the results show that the proposed scheme can attain better accuracy in comparison with the conventional multimodal fusion using latent semantic analysis as well as the single-modality verifications. The experiment on MATLAB shows the potential of the proposed scheme to attain the real-time performance for perceptual HCI applications.

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Algal blooms caused by cyanobacteria are characterized by two features with different time scales: one is seasonal outbreak and collapse of a bloom and the other is diurnal vertical migration. Our two-component mathematical model can simulate both phenomena, in which the state variables are nutrients and cyanobacteria. The model is a set of one-dimensional reaction-advection-diffusion equations, and temporal changes of these two variables are regulated by the following five factors: (1) annual variation of light intensity, (2) diurnal variation of light intensity, (3) annual variation of water temperature, (4) thermal stratification within a water column and (5) the buoyancy regulation mechanism. The seasonal change of cyanobacteria biomass is mainly controlled by factors, (1), (3) and (4), among which annual variations of light intensity and water temperature directly affect the maximum growth rate of cyanobacteria. The latter also contributes to formation of the thermocline during the summer season. Thermal stratification causes a reduction in vertical diffusion and largely prevents mixing of both nutrients and cyanobacteria between the epilimnion and the hypolimnion. Meanwhile, the other two factors, (2) and (5), play a significant role in diurnal vertical migration of cyanobacteria. A key mechanism of vertical migration is buoyancy regulation due to gas-vesicle synthesis and ballast formation, by which a quick reversal between floating and sinking becomes possible within a water column. The mechanism of bloom formation controlled by these five factors is integrated into the one-dimensional model consisting of two reaction-advection-diffusion equations.

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