Efficient advanced encryption standard implementation using lookup and normal basis

A new type of advanced encryption standard (AES) implementation using a normal basis is presented. The method is based on a lookup technique that makes use of inversion and shift registers, which leads to a smaller size of lookup for the S-box than its corresponding implementations. The reduction in the lookup size is based on grouping sets of inverses into conjugate sets which in turn leads to a reduction in the number of lookup values. The above technique is implemented in a regular AES architecture using register files, which requires less interconnect and area and is suitable for security applications. The results of the implementation are competitive in throughput and area compared with the corresponding solutions in a polynomial basis.

Mixed radix Reed-Muller expansions

The choice of radix is crucial for multi-valued logic synthesis. Practical examples, however, reveal that it is not always possible to find the optimal radix when taking into consideration actual physical parameters of multi-valued operations. In other words, each radix has its advantages and disadvantages. Our proposal is to synthesise logic in different radices, so it may benefit from their combination. The theory presented in this paper is based on Reed-Muller expansions over Galois field arithmetic. The work aims to firstly estimate the potential of the new approach and to secondly analyse its impact on circuit parameters down to the level of physical gates. The presented theory has been applied to real-life examples focusing on cryptographic circuits where Galois Fields find frequent application. The benchmark results show the approach creates a new dimension for the trade-off between circuit parameters and provides information on how the implemented functions are related to different radices.

Dynamic global security-aware synthesis using System-C

A dynamic global security-aware synthesis flow using the SystemC language is presented. SystemC security models are first specified at the system or behavioural level using a library of SystemC behavioural descriptions which provide for the reuse and extension of security modules. At the core of the system is incorporated a global security-aware scheduling algorithm which allows for scheduling to a mixture of components of varying security level. The output from the scheduler is translated into annotated nets which are subsequently passed to allocation, optimisation and mapping tools for mapping into circuits. The synthesised circuits incorporate asynchronous secure power-balanced and fault-protected components. Results show that the approach offers robust implementations and efficient security/area trade-offs leading to significant improvements in turnover.

FASCIOLA-HEPATICA - THE EFFECT OF THE MICROFILAMENT INHIBITOR CYTOCHALASIN-B ON THE ULTRASTRUCTURE OF THE ADULT FLUKE

The effect of the microfilament inhibitor cytochalasin B (10 and 100-mu-g/ml) on the ultrastructure of adult Fasciola hepatica was determined in vitro by scanning and transmission electron microscopy (SEM, TEM) using both intact flukes and tissue-slice material. SEM revealed that initial swelling of the tegument led to surface blebbing and limited areas of sloughing after 24 h treatment at 100-mu-g/ml. In the tegumental syncytium, basal accumulations of secretory bodies (especially T2s) were evident in the earlier time periods but declined with longer incubations, until few secretory bodies remained in the syncytium overall. Blebbing of the apical plasma membrane and occasional areas of breakdown and sloughing of the tegument were observed over longer periods of treatment at 100-mu-g/ml. In the tegumental cell bodies, the Golgi complexes gradually decreased in size and activity, and few secretory bodies were produced. In the later time periods, the cells assumed abnormal shapes, the cytoplasm shrinking in towards the nucleus. In the vitelline follicles, a random dispersion of shell protein globules was evident within the intermediate-type cells, rather than their being organized into distinct shell globule clusters. Disruption of this process was more severe at the higher concentration of 100-mu-g/ml and again was more evident in tissue-slice material. In the latter, after prolonged (12 h) exposure to cytochalasin B, the intermediate and mature vitelline cells were filled with loosely packed and expanded shell globule clusters, containing few shell protein globules. The mature vitelline cells continued to lay down "yolk" globules and glycogen deposits. Disruption of the network of processes from the nurse cells was evident at the higher concentration of cytochalasin. Spaces began to appear between the vitelline cells and grew larger with progressively longer incubation periods, and the cells themselves assumed abnormal shapes. A number of binucleate stem cells were observed in tissue-slice material at the longest incubation period (12 h).

Life history of the rare red alga Tsengia bairdii (=Platoma bairdii) (Nemastomataceae, Rhodophyta) from Scotland

A single thallus of the rare red seaweed Tsengia bairdii (Farlow) K. Fan et Y.Fan( Platoma bairdii (Farlow) Kuckuck) (Nemastomataceae) was collected on a subtidal pebble on the west coast of Scotland. The terete gelatinous axes, which were only 7 mm high, were monoecious. They bore numerous cystocarps and a few spermatangia, which represent the first observation of male structures in this genus. Released carpospores grew into expanded basal discs that gave rise to erect axes bearing irregularly cruciate tetrasporangia. irregularly cruciate to zonate tetrasporangia were also formed on these basal discs. Karyological studies on dividing tetrasporocytes showed about 25 bodies, identified as paired meiotic chromosomes on the basis of their size in comparison to mitotic and meiotic chromosomes in other red algal species. These observations confirm the isomorphic life history inferred from early field collections and show that this species is monoecious. Tsengia bairdii is an extremely rare seaweed in Europe - it seems to be confined to sublittoral cobbles and has a temporally patchy distribution.

A KARYOLOGICAL DEMONSTRATION OF MEIOSIS IN GELIDIUM-LATIFOLIUM (GELIDIACEAE, RHODOPHYTA) FROM IRELAND

A population of Gelidium latifolium (Greville) Bornet et Thuret (Rhodophyta) from Portstewart, County Antrim, Northern Ireland, was dominated by tetrasporophytes. When grown in culture, excised tips from 10 non-reproductive individuals all formed tetrasporangial branches. Chromosome counts in mitotic nuclei of vegetative cells from cultured tetrasporophytic apices were 58 +/- 4 chromosomes. In nuclei of dividing tetrasporocytes there were 29 +/- 2 larger bodies that were interpreted as paired meiotic chromosomes. Field-collected tetrasporophytes from Islandmagee. County Antrim. also showed approximately 29 pairs of chromosomes during meiosis in tetrasporocytes, This is the first report of meiosis in G. latifolium and the first direct demonstration of meiosis in this commercially important genus. In germinating tetraspores, the haploid nucleus initially divided prior to or during formation of the germination tube. The two daughter nuclei then underwent synchronous mitoses to form four haploid nuclei (n = 29 +/- 2), only one of which entered the germination tube. The sporeling survival rate was low, and few plants grew to maturity. The largest of these was diploid, with 55-58 chromosomes, and formed spermatangia after 14 months in culture. Other plants, which were abnormally bushy and densely branched, failed to reproduce. Since the most vigorous individual (and possibly also the other survivors) had apparently diploidized spontaneously during development, it is possible that the lack of gametophytes in the local G. latifolium population results from poor viability of haploid sporelings.

Managing SMT Resource Usage through Speculative Instruction Window Weighting

Simultaneous multithreading processors dynamically share processor resources between multiple threads. In general, shared SMT resources may be managed explicitly, for instance, by dynamically setting queue occupation bounds for each thread as in the DCRA and Hill-Climbing policies. Alternatively, resources may be managed implicitly; that is, resource usage is controlled by placing the desired instruction mix in the resources. In this case, the main resource management tool is the instruction fetch policy which must predict the behavior of each thread (branch mispredictions, long-latency loads, etc.) as it fetches instructions.

A profile-based tool for finding pipeline parallelism in sequential programs

Traditional static analysis fails to auto-parallelize programs with a complex control and data flow. Furthermore, thread-level parallelism in such programs is often restricted to pipeline parallelism, which can be hard to discover by a programmer. In this paper we propose a tool that, based on profiling information, helps the programmer to discover parallelism. The programmer hand-picks the code transformations from among the proposed candidates which are then applied by automatic code transformation techniques.

This paper contributes to the literature by presenting a profiling tool for discovering thread-level parallelism. We track dependencies at the whole-data structure level rather than at the element level or byte level in order to limit the profiling overhead. We perform a thorough analysis of the needs and costs of this technique. Furthermore, we present and validate the belief that programs with complex control and data flow contain significant amounts of exploitable coarse-grain pipeline parallelism in the program’s outer loops. This observation validates our approach to whole-data structure dependencies. As state-of-the-art compilers focus on loops iterating over data structure members, this observation also explains why our approach finds coarse-grain pipeline parallelism in cases that have remained out of reach for state-of-the-art compilers. In cases where traditional compilation techniques do find parallelism, our approach allows to discover higher degrees of parallelism, allowing a 40% speedup over traditional compilation techniques. Moreover, we demonstrate real speedups on multiple hardware platforms.

Speculative Return Address Stack Management Revisited

Branch prediction feeds a speculative execution processor core with instructions. Branch mispredictions are inevitable and have negative effects on performance and energy consumption. With the advent of highly accurate conditional branch predictors, nonconditional branch instructions are gaining importance.

Clustered indexing for branch predictors

As a result of resource limitations, state in branch predictors is frequently shared between uncorrelated branches. This interference can significantly limit prediction accuracy. In current predictor designs, the branches sharing prediction information are determined by their branch addresses and thus branch groups are arbitrarily chosen during compilation. This feasibility study explores a more analytic and systematic approach to classify branches into clusters with similar behavioral characteristics. We present several ways to incorporate this cluster information as an additional information source in branch predictors.

On generating set index functions for randomized caches

Caches hide the growing latency of accesses to the main memory from the processor by storing the most recently used data on-chip. To limit the search time through the caches, they are organized in a direct mapped or set-associative way. Such an organization introduces many conflict misses that hamper performance. This paper studies randomizing set index functions, a technique to place the data in the cache in such a way that conflict misses are avoided. The performance of such a randomized cache strongly depends on the randomization function. This paper discusses a methodology to generate randomization functions that perform well over a broad range of benchmarks. The methodology uses profiling information to predict the conflict miss rate of randomization functions. Then, using this information, a search algorithm finds the best randomization function. Due to implementation issues, it is preferable to use a randomization function that is extremely simple and can be evaluated in little time. For these reasons, we use randomization functions where each randomized address bit is computed as the XOR of a subset of the original address bits. These functions are chosen such that they operate on as few address bits as possible and have few inputs to each XOR. This paper shows that to index a 2(m)-set cache, it suffices to randomize m+2 or m+3 address bits and to limit the number of inputs to each XOR to 2 bits to obtain the full potential of randomization. Furthermore, it is shown that the randomization function that we generate for one set of benchmarks also works well for an entirely different set of benchmarks. Using the described methodology, it is possible to reduce the implementation cost of randomization functions with only an insignificant loss in conflict reduction.