Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking

In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching. © 2009 IEEE.

Development of dynamic structural testing to current state-of-the-art hybrid testing

Even though computational power used for structural analysis is ever increasing, there is still a fundamental need for testing in structural engineering, either for validation of complex numerical models or to assess material behaviour. In addition to analysis of structures using scale models, many structural engineers are aware to some extent of cyclic and shake-table test methods, but less so of ‘hybrid testing’. The latter is a combination of physical testing (e.g. hydraulic
actuators) and computational modelling (e.g. finite element modelling). Over the past 40 years, hybrid testing of engineering structures has developed from concept through to maturity to become a reliable and accurate dynamic testing technique. The hybrid test method provides users with some additional benefits that standard dynamic testing methods do not, and the method is more cost-effective in comparison to shake-table testing. This article aims to provide the reader with a basic understanding of the hybrid test method, including its contextual development and potential as a dynamic testing technique.

Compiler and Runtime Support for Hybrid Static/Dynamic Scheduling

One of the outstanding issues in parallel computing is the selection of task granularity. This work proposes a solution to the task granularity problem by lowering the overhead of the task scheduler and as such supporting very fine-grain tasks. Using a combination of static (compile-time) scheduling and dynamic (run-time) scheduling, we aim to make scheduling decisions as fast as with static scheduling while retaining the dynamic load- balancing properties of fully dynamic scheduling. We present an example application and discuss the requirements on the compiler and runtime system to realize hybrid static/dynamic scheduling.