164 resultados para deep architectures


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For over 50 years bridge plugs and cement have been used for well abandonment and work over and are still the material of choice. However the failures of cement abandonments using bridge plugs has been reported on many occasions, some of which have resulted in fatal consequences. A new patented product is designed to address the shortcomings associated with using bridge plugs and cement. The new developed tools use an alloy based on bismuth that is melted in situ using Thermite reaction. The tool uses the expansion properties of bismuth to seal the well. Testing the new technology in real field under more than 2 km deep sea water can be expensive. Virtual simulation of the new device under simulated thermal and mechanical environment can be achieved using nonlinear finite element method to validate the product and reduce cost. Experimental testing in the lab is performed to measure heat generated due to thermite reaction. Then, a sequential thermal mechanical explicit/implicit finite element solver is used to simulate the device under both testing lab and deep water conditions.

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We propose a data flow based run time system as an efficient tool for supporting execution of parallel code on heterogeneous architectures hosting both multicore CPUs and GPUs. We discuss how the proposed run time system may be the target of both structured parallel applications developed using algorithmic skeletons/parallel design patterns and also more "domain specific" programming models. Experimental results demonstrating the feasibility of the approach are presented. © 2012 World Scientific Publishing Company.

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Massively parallel networks of highly efficient, high performance Single Instruction Multiple Data (SIMD) processors have been shown to enable FPGA-based implementation of real-time signal processing applications with performance and
cost comparable to dedicated hardware architectures. This is achieved by exploiting simple datapath units with deep processing pipelines. However, these architectures are highly susceptible to pipeline bubbles resulting from data and control hazards; the only way to mitigate against these is manual interleaving of
application tasks on each datapath, since no suitable automated interleaving approach exists. In this paper we describe a new automated integrated mapping/scheduling approach to map algorithm tasks to processors and a new low-complexity list scheduling technique to generate the interleaved schedules. When applied to a spatial Fixed-Complexity Sphere Decoding (FSD) detector
for next-generation Multiple-Input Multiple-Output (MIMO) systems, the resulting schedules achieve real-time performance for IEEE 802.11n systems on a network of 16-way SIMD processors on FPGA, enable better performance/complexity balance than current approaches and produce results comparable to handcrafted implementations.

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Deep vein thrombosis (DVT) presents a significant risk for women requiring Caesarean section.
Venous thromboembolism (VTE) remains the leading direct cause of maternal death in the
UK and is the second most common cause of maternal death worldwide, accounting for 11%
of maternal deaths (RCOG 2009). This article uses a reflective cycle to explore the role of the
preoperative practitioner in the prevention of DVT for women undergoing elective Caesarean
section.

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