Children's serial recall errors: Implications for theories of short-term memory development

Three experiments examined developmental changes in serial recall of lists of 6 letters, with errors classified as movements, omissions, intrusions, or repetitions. In Experiments 1 and 2, developmental differences between groups of children aged from 7 to 11 years and adults were found in the pattern of serial recall errors. The errors of older participants were more likely to be movements than were those of younger participants, who made more intrusions and omissions. The number of repetition errors did not change with age, and this finding is interpreted in terms of a developmentally invariant postoutput response inhibition process. This interpretation was supported by the findings of Experiment 3, which measured levels of response inhibition in 7-, 9-, and 11-year-olds by comparing recall of lists with and without repeated items. Response inhibition remained developmentally invariant, although older children showed greater response facilitation (improved correct recall of adjacent repeated items). Group differences in the patterns of other errors are accounted for in terms of developmental changes in levels of output forgetting and changes in the efficiency of temporal encoding processes, (C) 2000 Academic Press.

Gender differences, responsiveness and memory of a potentially painful event in hermit crabs

Nonreflexive responses to a noxious event and prolonged memory are key criteria of a pain experience. In a previous study, hermit crabs, Pagurus bernhardus, that received a small electric shock within their shell often temporarily evacuated the shell and some groomed their abdomen and/or moved away from their vital resource. Most, however, returned to the shell. When offered a new shell 20 s later, shocked crabs were more likely than nonshocked crabs to approach and move into a new shell and did so more quickly (Elwood & Appel 2009, Animal Behaviour, 77, 1243-1246). Here we examined how increasing the time between the shock and the offering of a new shell influences the response. There was evidence of a memory of the aversive shock that lasted at least 1 day. Crabs tested after 30 min and 1 day were more likely to approach the shell and new shells were more likely to be taken 30 min after the shock. Shocked crabs approached the new shell more quickly and used fewer probes of the chelipeds prior to moving in and these results were stable over time and significant for specific times up to 1 day. Females were more likely than males to evacuate shells and did so after fewer shocks. These results extend previous work and demonstrate an extended memory of having been shocked. The findings are consistent with respect to criteria for pain that are accepted for vertebrates.

Memory-Centric Hardware Synthesis from Dataflow Models

Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues in terms of memory organisation and accesses when developing systems from these high level representations. Using a template matching design study, challenges such as modelling memory reuse and minimising buffer requirements are examined, yielding results with significantly less memory requirements and costly off-chip memory accesses.

SoC memory hierarchy derivation from dataflow graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.