82 resultados para custom


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Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bitwidth and data representation. This is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on OpenCL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. OpenCL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified OpenCL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3x faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

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In this paper we consider charging strategies that mitigate the impact of domestic charging of EVs on low-voltage distribution networks and which seek to reduce peak power by responding to time-ofday pricing. The strategies are based on the distributed Additive Increase and Multiplicative Decrease (AIMD) charging algorithms proposed in [5]. The strategies are evaluated using simulations conducted on a custom OpenDSS-Matlab platform for a typical low voltage residential feeder network. Results show that by using AIMD based smart charging 50% EV penetration can be accommodated on our test network, compared to only 10% with uncontrolled charging, without needing to reinforce existing network infrastructure. © Springer-Verlag Berlin Heidelberg 2013.

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The design and VLSI implementation of two key components of the class-IV partial response maximum likelihood channel (PR-IV) the adaptive filter and the Viterbi decoder are described. These blocks are implemented using parameterised VHDL modules, from a library of common digital signal processing (DSP) and arithmetic functions. Design studies, based on 0.6 micron 3.3V standard cell processes, indicate that worst case sampling rates of 49 mega-samples per second are achievable for this system, with proportionally high sampling rates for full custom designs and smaller dimension processes. Significant increases in the sampling rate, from 49 MHz to approximately 180 MHz, can be achieved by operating four filter modules in parallel, and this implementation has 50% lower power consumption than a pipelined filter operating at the same speed.

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With security and surveillance, there is an increasing need to be able to process image data efficiently and effectively either at source or in a large data networks. Whilst Field Programmable Gate Arrays have been seen as a key technology for enabling this, they typically use high level and/or hardware description language synthesis approaches; this provides a major disadvantage in terms of the time needed to design or program them and to verify correct operation; it considerably reduces the programmability capability of any technique based on this technology. The work here proposes a different approach of using optimised soft-core processors which can be programmed in software. In particular, the paper proposes a design tool chain for programming such processors that uses the CAL Actor Language as a starting point for describing an image processing algorithm and targets its implementation to these custom designed, soft-core processors on FPGA. The main purpose is to exploit the task and data parallelism in order to achieve the same parallelism as a previous HDL implementation but avoiding the design time, verification and debugging steps associated with such approaches.

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Purpose: To determine differences in overall tumor responses measured by volumetric assessment and bioluminescence imaging (BLI) following exposure to uniform and non-uniform radiation fields in an ectopic prostate tumor model.

Materials and methods: Bioluminescent human prostate tumor xenografts were established by subcutaneous implantation into male mice. Tumors were irradiated with uniform or non-uniform field configurations using conventional in vivo irradiation procedures performed using a 225 kVp generator with custom lead shielding. Tumor responses were measured using Vernier calipers and by BLI using an in vivo imaging system. Survival was defined as the time to quadroupling of pre-treatment tumor volume. 

Results: The correlation between BLI and tumor volume measurements was found to be different for un-irradiated (R = 0.61), uniformly irradiated (R = 0.34) and partially irradiated (R = 0.30) tumors. Uniformly irradiated tumors resulted in an average tumor growth delay of 60 days with median survival of 75 days, compared to partially irradiated tumors which showed an average growth delay of 24 days and median survival of 38 days. 

Conclusions: Correlation between BLI and tumor volume measurements is lower for partially irradiated tumors than those exposed to uniform dose distributions. The response of partially irradiated tumors suggests non-uniformity in response beyond physical dose distribution within the target volume. Dosimetric uncertainty associated with conventional in vivo irradiation procedures prohibits their ability to accurately determine tumor response to non-uniform radiation fields and stresses the need for image guided small animal radiation research platforms.

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Music for Sleeping & Waking Minds (2011-2012) is a new,overnight work in which four performers fall asleep while wearing custom designed EEG sensors which monitor their brainwave activity. The data gathered from the EEG sensors is applied in real time to different audio and image signal processing functions, resulting in continuously evolving multichannel sound environment and visual projection. This material serves as an audiovisual description of the individual and collective neuro physiological state of the ensemble. Audiences are invited to experience the work in different states of attention: while alert and asleep, resting and awakening.

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A novel manufacturing process for fabricating microneedle arrays (MN) has been designed and evaluated. The prototype is able to successfully produce 14 × 14 MN arrays and is easily capable of scale-up, enabling the transition from laboratory to industry and subsequent commercialisation. The method requires the custom design of metal MN master templates to produce silicone MN moulds using an injection moulding process. The MN arrays produced using this novel method was compared with centrifugation, the traditional method of producing aqueous hydrogel-forming MN arrays. The results proved that there was negligible difference between either methods, with each producing MN arrays with comparable quality. Both types of MN arrays can be successfully inserted in a skin simulant. In both cases the insertion depth was approximately 60% of the needle length and the height reduction after insertion was in both cases approximately 3%.

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Cyber-attacks against Smart Grids have been found in the real world. Malware such as Havex and BlackEnergy have been found targeting industrial control systems (ICS) and researchers have shown that cyber-attacks can exploit vulnerabilities in widely used Smart Grid communication standards. This paper addresses a deep investigation of attacks against the manufacturing message specification of IEC 61850, which is expected to become one of the most widely used communication services in Smart Grids. We investigate how an attacker can build a custom tool to execute man-in-the-middle attacks, manipulate data, and affect the physical system. Attack capabilities are demonstrated based on NESCOR scenarios to make it possible to thoroughly test these scenarios in a real system. The goal is to help understand the potential for such attacks, and to aid the development and testing of cyber security solutions. An attack use-case is presented that focuses on the standard for power utility automation, IEC 61850 in the context of inverter-based distributed energy resource devices; especially photovoltaic (PV) generators.

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Ionic liquid gel materials offer a way to further utilise ionic liquids in technological applications. Combining the controlled and directed assembly of gels, with the diverse applications of ionic liquids, enables the design of a heady combination of functional tailored materials, leading to the development of task specific / functional ionic liquid gels. This review introduces gels and gel classification, focusing on ionic liquid gels and their potential roles in a more sustainable future. Ionic liquid gels provide the ability to build functionality at every level, the solid component, the ionic liquid, and any incorporated active functional agents. This allows materials to be custom designed for a vast assortment of applications. This diverse class of materials has the potential to yield functional materials for green and sustainable chemistry, energy, electronics, medicine, food, cosmetics, and more. The discussion of the development of ionic liquid gel materials for applications in green and sustainable chemistry centres on uses of ionic liquid gels in catalysis and energy.

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Field programmable gate array devices boast abundant resources with which custom accelerator components for signal, image and data processing may be realised; however, realising high performance, low cost accelerators currently demands manual register transfer level design. Software-programmable ’soft’ processors have been proposed as a way to reduce this design burden but they are unable to support performance and cost comparable to custom circuits. This paper proposes a new soft processing approach for FPGA which promises to overcome this barrier. A high performance, fine-grained streaming processor, known as a Streaming Accelerator Element, is proposed which realises accelerators as large scale custom multicore networks. By adopting a streaming execution approach with advanced program control and memory addressing capabilities, typical program inefficiencies can be almost completely eliminated to enable performance and cost which are unprecedented amongst software-programmable solutions. When used to realise accelerators for fast fourier transform, motion estimation, matrix multiplication and sobel edge detection it is shown how the proposed architecture enables real-time performance and with performance and cost comparable with hand-crafted custom circuit accelerators and up to two orders of magnitude beyond existing soft processors.

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Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.

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Software-programmable `soft' processors have shown tremendous potential for efficient realisation of high performance signal processing operations on Field Programmable Gate Array (FPGA), whilst lowering the design burden by avoiding the need to design fine-grained custom circuit archi-tectures. However, the complex data access patterns, high memory bandwidth and computational requirements of sliding window applications, such as Motion Estimation (ME) and Matrix Multiplication (MM), lead to low performance, inefficient soft processor realisations. This paper resolves this issue, showing how by adding support for block data addressing and accelerators for high performance loop execution, performance and resource efficiency over four times better than current best-in-class metrics can be achieved. In addition, it demonstrates the first recorded real-time soft ME estimation realisation for H.263 systems.

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The increasing design complexity associated with modern Field Programmable Gate Array (FPGA) has prompted the emergence of 'soft'-programmable processors which attempt to replace at least part of the custom circuit design problem with a problem of programming parallel processors. Despite substantial advances in this technology, its performance and resource efficiency for computationally complex operations remains in doubt. In this paper we present the first recorded implementation of a softcore Fast-Fourier Transform (FFT) on Xilinx Virtex FPGA technology. By employing a streaming processing architecture, we show how it is possible to achieve architectures which offer 1.1 GSamples/s throughput and up to 19 times speed-up against the Xilinx Radix-2 FFT dedicated circuit with comparable cost.

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Introduction: Ca2+ ion is an important intracellular messenger essential for the regulation of various cellular functions including proliferation, differentiation and apoptosis. Transient Receptor Potential (TRP) channels are calcium permeable cationic channels that play important role in regulation of free intracellular calcium ([Ca2+]i) in response to thermal, physical and chemical stimuli. Ca2+ signalling in human dental pulp stem cells (hDPSCs) and the ion channels regulating Ca2+ are largely not known. Objectives: Investigate changes in [Ca2+]i and determine the ion channels that regulate calcium signalling in hDPSCs. Methods: DPSCs were derived from immature third molars and cells less than passage 6 were used in all the experiments. Changes in [Ca2+]i were studied with Fura2 calcium imaging. RNA was extracted from DPSCs and a panel of TRP channel gene expression was determined by qPCR employing custom designed FAM TRP specific primers and probes (Roche, UK) and the Light Cycler 480 Probes Master (Roche). Results: hDPSCs express gene transcripts for all TRP families including TRPV1, V2, V4, TRPA1, TRPC3, TRPC5, TRPC6, TRPM3, TRPM7 and TRPP2. Stimulation of cells with appropriate TRP channel agonist induced increase in [Ca2+]i and similar responses were obtained when cell were mechanically stimulated by membrane stretch with application of hypotonic solution. Conclusion: TRP channels mediate calcium signalling in hDPSCs that merit further investigation.

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Background: The transient receptor potential (TRP) ion channels play a critical role in sensory physiology, where they act as transducers of thermal, mechanical and chemical stimuli. We have previously shown the functional expression of several TRP channels by human odontoblast-like cells and proposed their significance in odontoblast sensory perception. Functional expression of the mechano-sensitiveTRPV2 channel by human odontoblasts would further support a role for TRP channels in odontoblast physiology. Objective: The objective of the current study was to determine the functional expression of TRPV2 by human odontoblasts. Methods: Human dental pulp cells were cultured in the presence of 2 mM β-glycerophoshate to induce an odontoblast phenotype. TRPV2 gene expression was determined by qPCR employing custom designed FAM TRPV2 specific primers and probes (Roche, UK) and the Light Cycler 480 Probes Master (Roche). TRPV2 protein expression was determined following SDS-PAGE and Western blotting of cell lysate preparations. Functional expression of TRPV2 was investigated by Ca2+ microfluorimetry. Results: qPCR data indicated robust expression of TRPV2 in odontoblast-like cells. Western blotting revealed a discrete immunoreactive protein band indicating expression of TRPV2 in cell lysates. In functional assays, the chemical agonist of TRPV2, cannabidiol, was shown to elicit [Ca2+]i transients, that were reduced to baseline in the presence of the TRPV2 antagonist Tranilast, suggesting channel functionality in odontoblast-like cells. Conclusion: These results provide the first evidence for the functional expression of TRPV2 in human odontoblast-like cells, providing further support for the role of TRP channels in odontoblast physiology.