From PASS 1 to YES to AND logic: building parallel processing into molecular logic gates by sequential addition of receptors

The synthesis and photophysical characterization of a novel molecular logic gate 4, operating in water, is demonstrated based on the competition between. fluorescence and photoinduced electron transfer (PET). It is constructed according to a 'fluorophore-spacer-receptor(1)-spacer-receptor(2)' format where anthracene is the. fluorophore, receptor(1) is a tertiary amine and receptor(2) is a phenyliminodiacetate ligand. Using only protons and zinc cations as the chemical inputs and. fluorescence as the output, 4 is demonstrated to be both a two-input AND and INH logic gate. When 4 is examined in context to the YES logic gates 1 and 2, and the two-input AND logic gate 3 and three-input AND logic gate 5, each with one or more of the following receptors including a tertiary amine, phenyliminodiacetate or benzo-15-crown-5 ether, logic gate 4 is the missing link in the homologous series. Collectively, the molecular logic gates 1-5 corroborate the PET 'fluorophore-spacer-receptor' model using chemical inputs and a light-signal output and provide insight into controlling the. fluorescence quantum yield of future PET-based molecular logic gates.

A programming model for BSP with partitioned synchronisation

A BSP superstep is a distributed computation comprising a number of simultaneously executing processes which may generate asynchronous messages. A superstep terminates with a barrier which enforces a global synchronisation and delivers all ongoing communications. Multilevel supersteps can utilise barriers in which subsets of processes, interacting through shared memories, are locally synchronised (partitioned synchronisation). In this paper a state-based semantics, closely related to the classical sequential programming model, is derived for distributed BSP with partitioned synchronisation.

Measuring conflict and agreement between two prioritized knowledge bases in possibilistic logic.

In this paper we investigate the relationship between two prioritized knowledge bases by measuring both the conflict and the agreement between them.First of all, a quantity of conflict and two quantities of agreement are defined. The former is shown to be a generalization of the well-known Dalal distance which is the hamming distance between two interpretations. The latter are, respectively, a quantity of strong agreement which measures the amount ofinformation on which two belief bases “totally” agree, and a quantity of weak agreement which measures the amount of information that is believed by onesource but is unknown to the other. All three quantity measures are based on the weighted prime implicant, which represents beliefs in a prioritized belief base. We then define a degree of conflict and two degrees of agreement based on our quantity of conflict and quantities of agreement. We also consider the impact of these measures on belief merging and information source ordering.

‘Child Care (Amendment) Bill 2009—An attempt to arbitrate on a system’s logic.’

The Child Care (Amendment) Bill was passed by the Seanad on 6th May 2010 and will shortly be enacted as legislation as the Child Care (Amendment) Act, 2010. The Bill, consisting of six Parts amends existing legislation relating to secure or ‘special care’ and makes some further amendments to the Child Care Act, 1991. The Act also provides for the dissolution of the Children Acts Advisory Board, a statutory body established in 2003, whose function was to advise the Minister on policy relating to specialist residential services (specifically Special Care Units) . This article examines the provisions of the Child Care Bill (2009) setting these in the context of current policy and previous legislation. It outlines that while the legislation outlines a detailed process for the application and administration of Special Care Orders, the provisions are weakened by the removal of external oversight mechanisms and the limitations placed on the role of the Guardian ad Litem.

Extruder Melt Temperature Control with Fuzzy Logic

In polymer extrusion, the delivery of a melt which is homogenous in composition and temperature is paramount for achieving high quality extruded products. However, advancements in process control are required to reduce temperature variations across the melt flow which can result in poor product quality. The majority of thermal monitoring methods provide only low accuracy point/bulk melt temperature measurements and cause poor controller performance. Furthermore, the most common conventional proportional-integral-derivative controllers seem to be incapable of performing well over the nonlinear operating region. This paper presents a model-based fuzzy control approach to reduce the die melt temperature variations across the melt flow while achieving desired average die melt temperature. Simulation results confirm the efficacy of the proposed controller.

Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs

Per-core scratchpad memories (or local stores) allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces, appropriate for scalable multicores, that combine the best of two worlds – the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized network interface (NI) functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multiword blocks through RDMA copy. Furthermore, we introduce event responses, as a technique that enables software configurable communication and synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, completion notifications for software selected sets of arbitrary size transfers, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and measure the logic overhead over a cache-only design for basic NI functionality to be less than 20%. We also evaluate the on-chip communication performance on the prototype, as well as the performance of synchronization functions with simulation of CMPs with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.