Identification of Small Signal Oscillation Mode Parameters from Simulated and Actual PMU Ringdown Data

This paper presents the practical use of Prony Analysis to identify small signal oscillation mode parameters from simulated and actual phasor measurement unit (PMU) ringdown data. A well-known two-area four-machine power system was considered as a study case while the latest PMU ringdown data were collected from a double circuit 275 kV main interconnector on the Irish power system. The eigenvalue analysis and power spectral density were also conducted for the purpose of comparison. The capability of Prony Analysis to identify the mode parameters from three different types of simulated PMU ringdown data has been shown successfully. Furthermore, the results indicate that the Irish power system has dominant frequency modes at different frequencies. However, each mode has good system damping.

Generation of cluster states in optomechanical quantum systems

We consider an optomechanical quantum system composed of a single cavity mode interacting with N mechanical resonators. We propose a scheme for generating continuous-variable graph states of arbitrary size and shape, including the so-called cluster states for universal quantum computation. The main feature of this scheme is that, differently from previous approaches, the graph states are hosted in the mechanical degrees of freedom rather than in the radiative ones. Specifically, via a 2N-tone drive, we engineer a linear Hamiltonian which is instrumental to dissipatively drive the system to the desired target state. The robustness of this scheme is assessed against finite interaction times and mechanical noise, confirming it as a valuable approach towards quantum state engineering for continuous-variable computation in a solid-state platform.

Memory-centric VDF Graph Transformations for Practical FPGA Implementation

Realising memory intensive applications such as image and video processing on FPGA requires creation of complex, multi-level memory hierarchies to achieve real-time performance; however commerical High Level Synthesis tools are unable to automatically derive such structures and hence are unable to meet the demanding bandwidth and capacity constraints of these applications. Current approaches to solving this problem can only derive either single-level memory structures or very deep, highly inefficient hierarchies, leading in either case to one or more of high implementation cost and low performance. This paper presents an enhancement to an existing MC-HLS synthesis approach which solves this problem; it exploits and eliminates data duplication at multiple levels levels of the generated hierarchy, leading to a reduction in the number of levels and ultimately higher performance, lower cost implementations. When applied to synthesis of C-based Motion Estimation, Matrix Multiplication and Sobel Edge Detection applications, this enables reductions in Block RAM and Look Up Table (LUT) cost of up to 25%, whilst simultaneously increasing throughput.