Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.

A programmable architecture for layered multimedia streams in IPv6 networks

A new configurable architecture is presented that offers multiple levels of video playback by accommodating variable levels of network utilization and bandwidth. By utilizing scalable MPEG-4 encoding at the network edge and using specific video delivery protocols, media streaming components are merged to fully optimize video playback for IPv6 networks, thus improving QoS. This is achieved by introducing “programmable network functionality” (PNF) which splits layered video transmission and distributes it evenly over available bandwidth, reducing packet loss and delay caused by out-of-profile DiffServ classes. An FPGA design is given which gives improved performance, e.g. link utilization, end-to-end delay, and that during congestion, improves on-time delivery of video frames by up to 80% when compared to current “static” DiffServ.

The Philosophy and Practice of Interpretivist Research in Entrepreneurship Quality, Validation, and Trust

Knowledge production in entrepreneurship requires inclusivity as well as diversity and pluralism in research perspectives and approaches. In this article, the authors address concerns about interpretivist research regarding validity, reliability, objectivity, generalizability, and communicability of results that militate against its more widespread acceptance. Following the nonfoundationalist argument that all observation is theory-laden, context specific, and that there are no external criteria against which to assess research design and execution and the data produced, the authors propose that quality must be internalized within the underlying research philosophy rather than something to be tested upon completion. This requires a shift from the notion of validity as an outcome to validation as a process. To elucidate this, they provide a guiding framework and present a case illustration that will assist an interpretivist entrepreneurship researcher to establish and demonstrate the quality of their work.

Philosophy, Social Hope and Democratic Criticism:Critical Theory for a Global Age

The attempt to connect philosophy and social hope has been one of the key distinguishing features of critical theory as a tradition of enquiry. This connection has been questioned forcefully from the perspective of a post-philosophical pragmatism, as articulated by Rorty. In this article I consider two strategies that have been adopted by critical theorists in seeking to reject Rorty's suggestion that we should abandon the attempt to ground social hope in philosophical reason. We consider argumentative strategies of the philosophical anthropologist and of the rational proceduralist. Once the exchanges between Rorty and these two strands of critical theory have been reconstructed and assessed, an alternative perspective emerges. It is argued that philosophical reasoning best helps to sustain social hope in a rapidly changing world when we consider it in terms of the practice of democratic criticism.

Burrow architecture and digging activity in the Cape dune mole rat

While females are traditionally thought to invest more time and energy into parental care than males, males often invest more resources into searching and displaying for mates, obtaining mates and in male-male conflict. Solitary subterranean mammals perform these activities in a particularly challenging niche, necessitating energetically expensive burrowing to both search for mates and forage for food. This restriction presumably affects males more than females as the former are thought to dig longer tunnels that cover greater distances to search for females. We excavated burrow systems of male and female Cape dune mole rats Bathyergus suillus the, largest truly subterranean mammal, to investigate whether male burrows differ from those of females in ways that reflect mate searching by males. We consider burrow architecture (length, internal dimensions, fractal dimension of tunnel systems, number of nesting chambers and mole mounds on the surface) in relation to mating strategy. Males excavated significantly longer burrow systems with higher fractal dimensions and larger burrow areas than females. Male burrow systems were also significantly farther from one another than females were from other females' burrow systems. However, no sex differences were evident in tunnel cross-sectional area, mass of soil excavated per mound, number of mounds produced per unit burrow length or mass of soil excavated per burrow system. Hence, while males may use their habitat differently from females, they do not appear to differ in the dimensions of the tunnels they create. Thus, exploration and use of the habitat differs between the sexes, which may be a consequence of sex differences in mating behaviour and greater demands for food.

Design and implementation of a field programmable CRC circuit architecture

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.