Exchange systems and style in the Central Mediterranean. 4500-1700 b.c..:Unpublished PhD. Cambridge University Library

Malone, C.A.T., 1986, Unpublished PhD, Cambridge University, Cambridge.

Copyright & Risk: Scoping the Wellcome Digital Library Project (peer reviewed)

Copyright & Risk: Scoping the Wellcome Digital Library is a comprehensive case study which assesses the merits of the risk-managed approach to copyright clearance adopted by the Wellcome Library in the course of their pilot digitisation project Codebreakers: Makers of Modern Genetics (http://wellcomelibrary.org/collections/digital-collections/makers-of-modern-genetics/#).

Methods for Optimal Work Instruction Delivery: Pictograms v Images

This paper focuses on quantifying the benefits of pictogram based instructions relative to static images for work instruction delivery. The assembly of a stiffened aircraft panel has been used as an exemplar for the work which seeks to address the challenge of identifying an instructional mode that can be location or language neutral while at the same time optimising assembly build times and maintaining build quality. Key performance parameters measured using a series of panel build experiments conducted by two separate groups were: overall build time, the number of subject references to instructional media, the number of build errors and the time taken to correct any mistakes. Overall build time for five builds for a group using pictogram instructions was about 20% lower than for the group using image based instructions. Also, the pictogram group made fewer errors. Although previous work identified that animated instructions result in optimal build times, the language neutrality of pictograms as well as the fact that they can be used without visualisation hardware mean that, on balance, they have broader applicability in terms of transferring assembly knowledge to the manufacturing environment.

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.