An optimal algorithm for low power multiplierless FIR filter design using chebychev criterion

In this paper, we propose a novel finite impulse response (FIR) filter design methodology that reduces the number of operations with a motivation to reduce power consumption and enhance performance. The novelty of our approach lies in the generation of filter coefficients such that they conform to a given low-power architecture, while meeting the given filter specifications. The proposed algorithm is formulated as a mixed integer linear programming problem that minimizes chebychev error and synthesizes coefficients which consist of pre-specified alphabets. The new modified coefficients can be used for low-power VLSI implementation of vector scaling operations such as FIR filtering using computation sharing multiplier (CSHM). Simulations in 0.25um technology show that CSHM FIR filter architecture can result in 55% power and 34% speed improvement compared to carry save multiplier (CSAM) based filters.

Process variation tolerant low power DCT architecture

2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain "good" image quality with Peak Signal to Noise Ratio(PSNR) > 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors would only appear from the long paths that are less contributive towards PSNR improvement, providing large improvement in power dissipation with small PSNR degradation. Results show that even under large process variation and supply voltage scaling (0.8V), there is a gradual degradation of image quality with considerable power savings (62.8%) for the proposed architecture when compared to existing implementations in 70 nm process technology.

Design methodology to trade off power, output quality and error resiliency: Application to color interpolation filtering

Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in. sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings.

Idealized Operation of Third-Harmonic-Peaking Class-Ef Power Amplifier with Extended Maximum Operating Frequency

A new variant of Class-EF power amplifier (PA), the so-called third-harmonic-peaking Class-EF, is presented. It inherits a soft-switching operation from the Class-E PA and a low peak switch voltage from the Class-F PA. More importantly, the new topology allows operations at higher frequencies and permits deployment of large transistors which is normally prohibited since they are always accompanied with high output capacitances. Using a simple transmission-line load network, the PA is synthesized to satisfy Class-EF impedances at fundamental frequency, third harmonic, and all even harmonics as well as to simultaneously provide an impedance matching to 50-Ω load.

Power Modeling and Capping for Heterogeneous ARM/FPGA SoCs

Low-power processors and accelerators that were originally designed for the embedded systems market are emerging as building blocks for servers. Power capping has been actively explored as a technique to reduce the energy footprint of high-performance processors. The opportunities and limitations of power capping on the new low-power processor and accelerator ecosystem are less understood. This paper presents an efficient power capping and management infrastructure for heterogeneous SoCs based on hybrid ARM/FPGA designs. The infrastructure coordinates dynamic voltage and frequency scaling with task allocation on a customised Linux system for the Xilinx Zynq SoC. We present a compiler-assisted power model to guide voltage and frequency scaling, in conjunction with workload allocation between the ARM cores and the FPGA, under given power caps. The model achieves less than 5% estimation bias to mean power consumption. In an FFT case study, the proposed power capping schemes achieve on average 97.5% of the performance of the optimal execution and match the optimal execution in 87.5% of the cases, while always meeting power constraints.

Secure D2D Communication in Large-Scale Cognitive Cellular Networks with Wireless Power Transfer

In this paper, we investigate secure device-to-device (D2D) communication in energy harvesting large-scale cognitive cellular networks. The energy constrained D2D transmitter harvests energy from multi-antenna equipped power beacons (PBs), and communicates with the corresponding receiver using the spectrum of the cellular base stations (BSs). We introduce a power transfer model and an information signal model to enable wireless energy harvesting and secure information transmission. In the power transfer model, we propose a new power transfer policy, namely, best power beacon (BPB) power transfer. To characterize the power transfer reliability of the proposed policy, we derive new closed-form expressions for the exact power outage probability and the asymptotic power outage probability with large antenna arrays at PBs. In the information signal model, we present a new comparative framework with two receiver selection schemes: 1) best receiver selection (BRS), and 2) nearest receiver selection (NRS). To assess the secrecy performance, we derive new expressions for the secrecy throughput considering the two receiver selection schemes using the BPB power transfer policies. We show that secrecy performance improves with increasing densities of PBs and D2D receivers because of a larger multiuser diversity gain. A pivotal conclusion is reached that BRS achieves better secrecy performance than NRS but demands more instantaneous feedback and overhead.

Small Signal Stability Performance of Power System during High Penetration of Wind Generation

The small signal stability of interconnected power systems is one of the important aspects that need to be investigated since the oscillations caused by this kind of instability have caused many incidents. With the increasing penetration of wind power in the power system, particularly doubly fed induction generator (DFIG), the impact on the power system small signal stability performance should be fully investigated. Because the DFIG wind turbine integration is through a fast action converter and associated control, it does not inherently participate in the electromechanical small signal oscillation. However, it influences the small signal stability by impacting active power flow paths in the network and replacing synchronous generators that have power system stabilizer (PSS). In this paper, the IEEE 39 bus test system has been used in the analysis. Furthermore, four study cases and several operation scenarios have been conducted and analysed. The selective eigenvalue Arnoldi/lanczos's method is used to obtain the system eigenvalue in the range of frequency from 0.2 Hz to 2 Hz which is related to electromechanical oscillations. Results show that the integration of DFIG wind turbines in a system during several study cases and operation scenarios give different influence on small signal stability performance.

New multi-stage DC-DC converters for grid-connected photovoltaic systems

Renewable energy is high on international and national agendas. Currently, grid-connected photovoltaic (PV) systems are a popular technology to convert solar energy into electricity. Existing PV panels have a relatively low and varying output voltage so that the converter installed between the PVs and the grid should be equipped with high step-up and versatile control capabilities. In addition, the output current of PV systems is rich in harmonics which affect the power quality of the grid. In this paper, a new multi-stage hysteresis control of a step-up DC-DC converter is proposed for integrating PVs into a single-phase power grid. The proposed circuitry and control method is experimentally validated by testing on a 600W prototype converter. The developed technology has significant economic implications and could be applied to many distributed generation (DG) systems, especially for the developing countries which have a large number of small PVs connected to their single-phase distribution network. 

New SR drive with integrated charging capacity for plug-in hybrid electric vehicles (PHEVs)

Plug-in hybrid electric vehicles (PHEVs) provide much promise in reducing greenhouse gas emissions and, thus, are a focal point of research and development. Existing on-board charging capacity is effective but requires the use of several power conversion devices and power converters, which reduce reliability and cost efficiency. This paper presents a novel three-phase switched reluctance (SR) motor drive with integrated charging functions (including internal combustion engine and grid charging). The electrical energy flow within the drivetrain is controlled by a power electronic converter with less power switching devices and magnetic devices. It allows the desired energy conversion between the engine generator, the battery, and the SR motor under different operation modes. Battery-charging techniques are developed to operate under both motor-driving mode and standstill-charging mode. During the magnetization mode, the machine's phase windings are energized by the dc-link voltage. The power converter and the machine phase windings are controlled with a three-phase relay to enable the use of the ac-dc rectifier. The power converter can work as a buck-boost-type or a buck-type dc-dc converter for charging the battery. Simulation results in MATLAB/Simulink and experiments on a 3-kW SR motor validate the effectiveness of the proposed technologies, which may have significant economic implications and improve the PHEVs' market acceptance

Real-time temperature estimation for power MOSFETs considering thermal aging effects

This paper presents a novel real-time power-device temperature estimation method that monitors the power MOSFET's junction temperature shift arising from thermal aging effects and incorporates the updated electrothermal models of power modules into digital controllers. Currently, the real-time estimator is emerging as an important tool for active control of device junction temperature as well as online health monitoring for power electronic systems, but its thermal model fails to address the device's ongoing degradation. Because of a mismatch of coefficients of thermal expansion between layers of power devices, repetitive thermal cycling will cause cracks, voids, and even delamination within the device components, particularly in the solder and thermal grease layers. Consequently, the thermal resistance of power devices will increase, making it possible to use thermal resistance (and junction temperature) as key indicators for condition monitoring and control purposes. In this paper, the predicted device temperature via threshold voltage measurements is compared with the real-time estimated ones, and the difference is attributed to the aging of the device. The thermal models in digital controllers are frequently updated to correct the shift caused by thermal aging effects. Experimental results on three power MOSFETs confirm that the proposed methodologies are effective to incorporate the thermal aging effects in the power-device temperature estimator with good accuracy. The developed adaptive technologies can be applied to other power devices such as IGBTs and SiC MOSFETs, and have significant economic implications. 

Complete control of high-harmonic generation for high average power applications

We present a new dual-gas multi-jet HHG source which can be perfectly controlled via phasematching of the long and short trajectory contributions and is applicable for high average power driver laser systems. © 2011 Optical Society of America.

Localization Algorithm Performance in Ultra Low Power Active RFID Based Patient Tracking

Indoor personnel localization research has generated a range of potential techniques and algorithms. However, these typically do not account for the influence of the user's body upon the radio channel. In this paper an active RFID based patient tracking system is demonstrated and three localization algorithms are used to estimate the location of a user within a modern office building. It is shown that disregarding body effects reduces the accuracy of the algorithms' location estimates and that body shadowing effects create a systematic position error that estimates the user's location as closer to the RFID reader that the active tag has line of sight to.

Asset Tracking in Critical Power Communications Infrastructures using Passive Techniques

Active network scanning injects traffic into a network and observes responses to draw conclusions about the network. Passive network analysis works by looking at network meta data or by analyzing traffic as it traverses a fixed point on the network. It may be infeasible or inappropriate to scan critical infrastructure networks. Techniques exist to uniquely map assets without resorting to active scanning. In many cases, it is possible to characterize and identify network nodes by passively analyzing traffic flows. These techniques are considered in particular with respect to their application to power industry critical infrastructure.

Pre-Processing Power Traces to Defeat Random Clocking Countermeasures

We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the AES rounds. It is demonstrated that the merged round patterns can be pre-processed to identify and extract the individual round amplitudes, enabling a successful power analysis attack. We show that the requirement of the random clocking countermeasure to provide a varying execution time between processing rounds can be exploited to select a sub-set of data where sufficient current decay has occurred, further improving the attack. In comparison with the countermeasure's estimated security of 3 million traces from an integration attack, we show that through application of our proposed techniques that the countermeasure can now be broken with as few as 13k traces.

Irish Power System Primary Frequency Response Metrics during Different System Non Synchronous Penetrations.

This paper discusses the use of primary frequency response metrics to assess the dynamics of frequency disturbance data with the presence of high system non synchronous penetration (SNSP) and system inertia variation. The Irish power system has been chosen as a study case as it experiences a significant level of SNSP from wind turbine generation and imported active power from HVDC interconnectors. Several recorded actual frequency disturbances were used in the analysis. These data were measured and collected from the Irish power system from October 2010 to June 2013. The paper has shown the impact of system inertia and SNSP variation on the performance of primary frequency response metrics, namely: nadir frequency, rate of change of frequency, inertial and primary frequency response.