Automatic FPGA Synthesis of Memory Intensive C-based Kernels

Realising high performance image and signal processing
applications on modern FPGA presents a challenging implementation problem due to the large data frames streaming through these systems. Specifically, to meet the high bandwidth and data storage demands of these applications, complex hierarchical memory architectures must be manually specified
at the Register Transfer Level (RTL). Automated approaches which convert high-level operation descriptions, for instance in the form of C programs, to an FPGA architecture, are unable to automatically realise such architectures. This paper
presents a solution to this problem. It presents a compiler to automatically derive such memory architectures from a C program. By transforming the input C program to a unique dataflow modelling dialect, known as Valved Dataflow (VDF), a mapping and synthesis approach developed for this dialect can
be exploited to automatically create high performance image and video processing architectures. Memory intensive C kernels for Motion Estimation (CIF Frames at 30 fps), Matrix Multiplication (128x128 @ 500 iter/sec) and Sobel Edge Detection (720p @ 30 fps), which are unrealisable by current state-of-the-art C-based synthesis tools, are automatically derived from a C description of the algorithm.

64-point Fourier transform chip for digital television applications

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.

A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.

Betwixt spaces: Students’ accounts of turning point experiences in first-year transitions

'Not belonging' is becoming a prevalent theme within accounts of the first-year student experience at university. In this study the notion of not belonging is extended by assuming a more active role for the idea of liminality in a student's transition into the university environments of academic and student life. In doing so, the article suggests that the transition between one place (home) and another (university) can result in an 'in-between-ness' - a betwixt space. Through an interpretative methodology, the study explores how students begin to move from this betwixt space into feeling like fully-fledged members of university life. It is concluded that there is a wide range of turning points associated with the students' betwixt transition, which shapes, alters or indeed accentuates the ways in which they make meaningful connections with university life. Moreover, transitional turning point experiences reveal a cast of characters and symbolic objects; capture contrasting motivations and evolving relationships; display multiple trajectories of interpersonal tensions and conflicts; highlight discontinuities as well as continuities; and together, simultaneously liberate and constrain the students' transition into university life.

Molecular dynamics simulation model for the quantitative assessment of tool wear during single point diamond turning of cubic silicon carbide

Silicon carbide (SiC) is a material of great technological interest for engineering applications concerning hostile environments where silicon-based components cannot work (beyond 623 K). Single point diamond turning (SPDT) has remained a superior and viable method to harness process efficiency and freeform shapes on this harder material. However, it is extremely difficult to machine this ceramic consistently in the ductile regime due to sudden and rapid tool wear. It thus becomes non trivial to develop an accurate understanding of tool wear mechanism during SPDT of SiC in order to identify measures to suppress wear to minimize operational cost.

In this paper, molecular dynamics (MD) simulation has been deployed with a realistic analytical bond order potential (ABOP) formalism based potential energy function to understand tool wear mechanism during single point diamond turning of SiC. The most significant result was obtained using the radial distribution function which suggests graphitization of diamond tool during the machining process. This phenomenon occurs due to the abrasive processes between these two ultra hard materials. The abrasive action results in locally high temperature which compounds with the massive cutting forces leading to sp3–sp2 order–disorder transition of diamond tool. This represents the root cause of tool wear during SPDT operation of cubic SiC. Further testing led to the development of a novel method for quantitative assessment of the progression of diamond tool wear from MD simulations.

GELIFICATION - A SIMPLE AND EFFICIENT METHOD FOR ON-CHIP STORAGE OF REAGENTS: TOWARDS LAB-ON-A-CHIP SYSTEMS FOR POINT-OF-CARE DIAGNOSTICS

In this study, we describe a simple and efficient method for on-chip storage of reagents for point-of-care (POC) diagnostics. The method is based on gelification of all reagents required for on-chip PCR-based diagnostics as a ready-to-use product. The result reported here is a key step towards the development of a ready and easy to use fully integrated Lab-on-a-chip (LOC) system for fast, cost-effective and efficient POC diagnostics analysis.