Liquid source misted chemical deposition process of three-dimensional nano-ferroelectrics with substrate heating

A modification of liquid source misted chemical deposition process (LSMCD) with heating mist and substrate has developed, and this enabled to control mist penetrability and fluidity on sidewalls of three-dimensional structures and ensure step coverage. A modified LSMCD process allowed a combinatorial approach of Pb(Zr,Ti)O-3 (PZT) thin films and carbon nanotubes (CNTs) toward ultrahigh integration density of ferroelectric random access memories (FeRAMs). The CNTs templates were survived during the crystallization process of deposited PZT film onto CNTs annealed at 650 degrees C in oxygen ambient due to a matter of minute process, so that the thermal budget is quite small. The modified LSMCD process opens up the possibility to realize the nanoscale capacitor structure of ferroelectric PZT film with CNTs electrodes toward ultrahigh integration density FeRAMs.

Packet classification by multi-level cutting of the classification space

Traditionally, the Internet provides only a “best-effort” service, treating all packets going to the same destination equally. However, providing differentiated services for different users based on their quality requirements is increasingly becoming a demanding issue. For this, routers need to have the capability to distinguish and isolate traffic belonging to different flows. This ability to determine the flow each packet belongs to is called packet classification. Technology vendors are reluctant to support algorithmic solutions for classification due to their nondeterministic performance. Although content addressable memories (CAMs) are favoured by technology vendors due to their deterministic high-lookup rates, they suffer from the problems of high-power consumption and high-silicon cost. This paper provides a new algorithmic-architectural solution for packet classification that mixes CAMs with algorithms based on multilevel cutting of the classification space into smaller spaces. The provided solution utilizes the geometrical distribution of rules in the classification space. It provides the deterministic performance of CAMs, support for dynamic updates, and added flexibility for system designers.

Memory retrieval as temporal discrimination

Temporal distinctiveness models of memory retrieval claim that memories are organised partly in terms of their positions along a temporal dimension, and suggest that memory retrieval involves temporal discrimination. According to such models the retrievability of memories should be related to the discriminability of their temporal distances at the time of retrieval. This prediction is tested directly in three pairs of experiments that examine (a) memory retrieval and (b) identification of temporal durations that correspond to the temporal distances of the memories. Qualitative similarities between memory retrieval and temporal discrimination are found in probed serial recall (Experiments 1 and 2), immediate and delayed free recall (Experiments 3 and 4) and probed serial recall of grouped lists (Experiments 5 and 6). The results are interpreted as consistent with the suggestion that memory retrieval is indeed akin to temporal discrimination. (C) 2008 Elsevier Inc. All rights reserved.

SoC memory hierarchy derivation from dataflow graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.

A programming model for BSP with partitioned synchronisation

A BSP superstep is a distributed computation comprising a number of simultaneously executing processes which may generate asynchronous messages. A superstep terminates with a barrier which enforces a global synchronisation and delivers all ongoing communications. Multilevel supersteps can utilise barriers in which subsets of processes, interacting through shared memories, are locally synchronised (partitioned synchronisation). In this paper a state-based semantics, closely related to the classical sequential programming model, is derived for distributed BSP with partitioned synchronisation.

History, an Exit Strategy: The Retrofuture Fabulations of kara lynch

A cartographer constructs a map of an individual creative history, that of the American artist kara lynch, as it emerges in connection to a collective history of African American cultural expression. Positioning history as complex, dynamic systems of interwoven memory networks, the map follows lynch’s traversals through various “zones of cultural haunting”: places where collective memories made invisible through systematic processes of cultural erasure may be recovered and revived. Through these traversals, which are inspired by lynch’s “forever project” Invisible, the map covers such terrains as haunted narratives, mechanisms of abstraction and coding within African American media production, water as an informational technology, the distribution of memory in blood, the dialectics of materiality and immateriality that frame considerations of black subjectivity, and the possibility that place of music might not be the site of sound but instead the social production of memory.

Connected Life Courses:Influences on and Experiences of 'Midlife' In-Migration to Rural Areas

This paper aims to contribute to the theorisation of midlife migration into rural areas. Although the factors influencing migration are known to be variable at different stages of a person's life, much less well understood is how migration decisions at different stages of the life course are connected and how post-migration experiences may be influenced by an earlier life course stage. We argue that midlife migration decisions are the product of the migrant's lifetime experiences and influences up until that stage in their life alongside their expectations and aspirations for future life course stages. Using a case study of the Glens of Antrim (Northern Ireland), this paper specifically demonstrates the role of childhood memories to explain midlife migration to a rural area. In doing so, it argues that some findings more commonly associated with second-generation transnational migration are also equally relevant to migration within the UK. Roots migration and place attachment alongside the midlife migrant's post-migration sense of belonging and permanency are found to be influenced by the migrant's earlier memories, behaviours, and experiences.

Instituting order: the limitations of Nasser’s post-colonial planning visions for Cairo in the case of the indigenous quarter of Bulaq (1952–1970)

This paper investigates the limitations of postcolonial planning practices that aimed to modernise Cairo’s urban spaces during Gamal Abdel Nasser rule (1952–70). Following the Free Officers revolution of 1952, ambition to display urban order through forceful change in the city’s built environment was in action. Nasser’s visions of modernity were explicit in a series of attempts to reshape several prime locations in central Cairo, which included the old traditional waterfront quarter, in Bulaq Abul Ela. An analysis of the Bulaq planning scheme drafted in 1966 reveals insights into how notions of order were spatialised to integrate with Cairo’s complex urban fabric. The official plans to regularise Bulaq also strongly demonstrates how this was a top-down, centralised process in terms of governance, with full utilisation of state resources, namely the military and the media. From a wider perspective, planning practices under Nasser demonstrated an evident break with the past to eliminate memories of colonisation and disorder. Drawing on original resources, archival material, meeting minutes and maps of this historical but dilapidated quarter of Cairo, this paper gives an insight into how Nasser’s government attempted to convey a sense of order in a revolutionary country without, however, having an understanding of order as a coherent, multilayered and sequential process of change.

Accelerating Multiple Sequence Alignment with the Cell BE Processor

The Cell Broadband Engine (BE) Architecture is a new heterogeneous multi-core architecture targeted at compute-intensive workloads. The architecture of the Cell BE has several features that are unique in high-performance general-purpose processors, most notably the extensive support for vectorization, scratch pad memories and explicit programming of direct memory accesses (DMAs) and mailbox communication. While these features strongly increase programming complexity, it is generally claimed that significant speedups can be obtained by using Cell BE processors. This paper presents our experiences with using the Cell BE architecture to accelerate Clustal W, a bio-informatics program for multiple sequence alignment. We report on how we apply the unique features of the Cell BE to Clustal W and how important each is in obtaining high performance. By making extensive use of vectorization and by parallelizing the application across all cores, we demonstrate a speedup of 24.4 times when using 16 synergistic processor units on a QS21 Cell Blade compared to single-thread execution on the power processing unit. As the Cell BE exploits a large number of slim cores, our highly optimized implementation is just 3.8 times faster than a 3-thread version running on an Intel Core2 Duo, as the latter processor exploits a small number of fat cores.

XOR-based hash functions

Bank conflicts can severely reduce the bandwidth of an interleaved multibank memory and conflict misses increase the miss rate of a cache or a predictor. Both occurrences are manifestations of the same problem: Objects which should be mapped to different indices are accidentally mapped to the same index. Suitable chosen hash functions can avoid conflicts in each of these situations by mapping the most frequently occurring patterns conflict-free. A particularly interesting class of hash functions are the XOR-based hash functions, which compute each set index bit as the exclusive-or of a subset of the address bits. When implementing an XOR-based hash function, it is extremely important to understand what patterns are mapped conflict-free and how a hash function can be constructed to map the most frequently occurring patterns without conflicts. Hereto, this paper presents two ways to reason about hash functions: by their null space and by their column space. The null space helps to quickly determine whether a pattern is mapped conflict-free. The column space is more useful for other purposes, e. g., to reduce the fan-in of the XOR-gates without introducing conflicts or to evaluate interbank dispersion in skewed-associative caches. Examples illustrate how these ideas can be applied to construct conflict-free hash functions.

On generating set index functions for randomized caches

Caches hide the growing latency of accesses to the main memory from the processor by storing the most recently used data on-chip. To limit the search time through the caches, they are organized in a direct mapped or set-associative way. Such an organization introduces many conflict misses that hamper performance. This paper studies randomizing set index functions, a technique to place the data in the cache in such a way that conflict misses are avoided. The performance of such a randomized cache strongly depends on the randomization function. This paper discusses a methodology to generate randomization functions that perform well over a broad range of benchmarks. The methodology uses profiling information to predict the conflict miss rate of randomization functions. Then, using this information, a search algorithm finds the best randomization function. Due to implementation issues, it is preferable to use a randomization function that is extremely simple and can be evaluated in little time. For these reasons, we use randomization functions where each randomized address bit is computed as the XOR of a subset of the original address bits. These functions are chosen such that they operate on as few address bits as possible and have few inputs to each XOR. This paper shows that to index a 2(m)-set cache, it suffices to randomize m+2 or m+3 address bits and to limit the number of inputs to each XOR to 2 bits to obtain the full potential of randomization. Furthermore, it is shown that the randomization function that we generate for one set of benchmarks also works well for an entirely different set of benchmarks. Using the described methodology, it is possible to reduce the implementation cost of randomization functions with only an insignificant loss in conflict reduction.

Randomized caches for power-efficiency

Embedded processors are used in numerous devices executing dedicated applications. This setting makes it worthwhile to optimize the processor to the application it executes, in order to increase its power-efficiency. This paper proposes to enhance direct mapped data caches with automatically tuned randomized set index functions to achieve that goal. We show how randomization functions can be automatically generated and compare them to traditional set-associative caches in terms of performance and energy consumption. A 16 kB randomized direct mapped cache consumes 22% less energy than a 2-way set-associative cache, while it is less than 3% slower. When the randomization function is made configurable (i.e., it can be adapted to the program), the additional reduction of conflicts outweighs the added complexity of the hardware, provided there is a sufficient amount of conflict misses.

Highly accurate and efficient evaluation of randomising set index functions

Randomising set index functions can reduce the number of conflict misses in data caches by spreading the cache blocks uniformly over all sets. Typically, the randomisation functions compute the exclusive ors of several address bits. Not all randomising set index functions perform equally well, which calls for the evaluation of many set index functions. This paper discusses and improves a technique that tackles this problem by predicting the miss rate incurred by a randomisation function, based on profiling information. A new way of looking at randomisation functions is used, namely the null space of the randomisation function. The members of the null space describe pairs of cache blocks that are mapped to the same set. This paper presents an analytical model of the error made by the technique and uses this to propose several optimisations to the technique. The technique is then applied to generate a conflict-free randomisation function for the SPEC benchmarks. (C) 2003 Elsevier Science B.V. All rights reserved.

Norberg-Schulz’ Elements of Space in Dark City

Alex Proyas' science fiction film Dark City (1998) puts forth questions about the building process of a city. The aliens in the film constantly alter each street, building and room to create the right environment for humans to dwell. The ‘strangers’ believe that they need to study humans in their spaces to understand human nature. They use bits and pieces of people's memories to reconstruct the city.

Christian Norberg-Schulz identifies four elements of space: physical, perceptual, existential and conceptual. Physical space is physical existence as it is. Perceptual space is the temporary space the user perceives. Existential space, for instance, the meaning of the concept of home, is abstract and permanent; it does not change with changing conditions. Finally, conceptual space, in his spatial philosophy, is the space concept of specialists like architects, economists and mathematicians.

This article analyses the future noir environment of Dark City from a spatial perspective. The notion of building is studied as to physical, perceptual, existential and conceptual spaces of Norberg-Schulz through concepts of home, identity, belonging, and alienation with reference to the architecture of the city.